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The damage induced by CO2 and O2 plasmas to an ultra low-k (ULK) dielectric film with a dielectric constant (κ) of 2.2 was investigated. The dielectric constant was observed to increase due to methyl depletion, moisture uptake, and surface densification. A gap structure was used to delineate the role of ions, photons and radicals in inducing the damage, where the experimental variables included an optical mask (MgF2, fused silica, and Si), a gap height, an inductively coupled plasma power source, a bias power on the bottom electrode, variable chamber pressure, and variable substrate temperature. The plasma radical density distribution inside the gap between the optical mask and the ULK film was simulated. The simulation was based on radical diffusion, reaction, and recombination inside the gap. The experimental results and the numerical simulation showed that the oxygen radicals played an important role in plasma induced damage which was found to be proportional to the oxygen radical density and enhanced byvacuum ultraviolet (VUV) photon radiation. Under certain experimental conditions, ion bombardment can induce surface densification and suppress radical diffusion. The role of UV and VUV photons in induced damage was investigated with Ar plasma using the gap structure and it was found that the photons can induce surface damage directly.

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A high reliability Metal-Insulator-Metal capacitor integrated into a 0.18 ym CMOS foundry technology using Copper interconnects is discussed. Integration solutions specific to Copper processing are described and process yield and reliability results are presented on 0.72 fF/pm2 capacitors. Performance and reliability metrics are shown to be comparable to those formed on Aluminum technologies.

The development of DRAM at IBM produced many novel processes and sophisticated analysis methods. Improvements in lithography and innovative process features reduced the cell size by a factor of 18.8 in the time between the 4Mb and 256Mb generations. The original substrate piate trench cell used in the 4Mb chip is still the basis of the 256Mb technology being developed today. This paper describes some of the more important and interesting innovations introduced in IBM CMOS DRAMs. Among them, shallow-trench isolation, 1-line and deep-UV (DUV) lithography, titanium salicidation, tungsten stud contacts, retrograde n-well, and planarized bacl(-end-ofline (BEOL) technology are core elements of current state-of-the-art logic technology described In other papers in this issue. The DRAM specific features described are borderless contacts, the trench capacitor, trench-isolated cell devices, and the "strap." Finally, the methods for study and control of leakage mechanisms which degrade DRAM retention time are described.^Copyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted witiiout payment of royalty provided tliat (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.

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Resist etch-back SiO2 planarization involving a pattern density compensation mask is described for line-space patterns of various dimensions extending to half-micron feature sizes. An empirical model is used to describe the positional dependence of planarization film thickness upon feature density within an array pattern. Design considerations related to the usage of the planarization "block mask" are discussed, a suitable etch condition is specified, and the planarization etchback method is used to achieve long-range, or global planarization.