The evolution of IBM CMOS DRAM technology

Adler, E.L.; DeBrosse, J.; Geissler, S.; Holmes, Steven J.; Jaffe, M. J.; Johnson, J. B.; Koburger, Charles W.; Lasky, J. B.; Lloyd, Bryn; Miles, G. L.; Nakos, J.; Noble, W.; Voldman, Steven H.; Armacost, M.; Ferguson, Richard A.

doi:10.1147/rd.391.0167

Cited by 50 publications

(18 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some DRAM manufacturers use polysilicon filled trench capacitor as a storage node (2). In this case, polysilicon recess processes play an important role in the overall process flow.…”

Section: Polysilicon Recess In Dram Trench Capacitorsmentioning

confidence: 99%

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques

Kaplita

Schmitz

Ranade

et al. 1999

Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V

View full text Add to dashboard Cite

The planarization and recessing of polysilicon to form a plug are processes of increasing importance in silicon IC fabrication. While this technology has been developed and applied to DRAM technology using Trench Storage Capacitors, the need for such processes in other IC applications (i.e. polysilicon studs) has increased. Both planarization and recess processes usually have stringent requirements on etch rate, recess uniformity, and selectivity to underlying films. Additionally, both processes generally must be isotropic, yet must not expand any seams that might be present in the polysilicon fill. These processes should also be insensitive to changes in exposed silicon area (pattern factor) on the wafer. A SF6 plasma process in a polysilicon DPS (Decoupled Plasma Source) reactor has demonstrated the capability of achieving the above process requirements for both plananzation and recess etch. The SF6 process in the decoupled plasma source reactor exhibited less sensitivity to pattern factor than in other types of reactors. Control of these planarization and recess processes requires two endpoint systems to work sequentially in the same recipe: one for monitoring the endpoint when blanket polysilicon (100% Si loading) is being planarized and one for monitoring the recess depth while the plug is being recessed (<10% Si loading). The planarization process employs an optical emission endpoint system (OES). An interferometric endpoint system (IEP), capable ofmomtonng lateral interference, is used for detennining the recess depth. The ability ofusing either or both systems is required to make these plug processes manufacturable. Measuring the recess depth resulting from the recess process can be difficult, costly and time-consuming. An Atomic Force Microscope (AFM) can greatly alleviate these problems and can serve as a critical tool in the development of recess processes.

show abstract

“…Some DRAM manufacturers use polysilicon filled trench capacitor as a storage node (2). In this case, polysilicon recess processes play an important role in the overall process flow.…”

Section: Polysilicon Recess In Dram Trench Capacitorsmentioning

confidence: 99%

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques

Kaplita

Schmitz

Ranade

et al. 1999

Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V

View full text Add to dashboard Cite

show abstract

“…GIDL is induced by band-to-band tunneling effect in strong accumulation mode and generated in the gate-to-drain overlap region. This leakage current component has been observed in DRAM trench transistor cells and in EEPROM memory cells and is identified as the main leakage mechanism of discharging the storage nodes in sub-micron dynamic logic [1][2][3]. This paper presents test results of abnormally high leakage current (∼0.1 -1 mA) observed in a digital ASIC.…”

Section: Introductionmentioning

confidence: 88%

“…al. [1] suggested that the poly-silicon line should have finite spacing from this interface ( Figure 5). …”

Section: Leakage Current At Locos Isolation Edgementioning

confidence: 99%

Contribution of gate induced drain leakage to overall leakage and yield loss in digital submicron VLSI circuits

Semenov

Pradzynski²,

Sachdev³

2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580)

View full text Add to dashboard Cite

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35 -µm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

show abstract

“…Among many known lealcage currents, the junction leakage current from the storage node is known to be the major leakage mechanism [12]. Due to local process variations, It varies among cells, resultmg in fluctuations oft RET among the cells [15,5]. Studies have showed that the log^itREr) of the cells follows a bimodal distribution, akin to the one shown in Figure 1.…”

Section: N Refresh In Conventional Drammentioning

confidence: 99%

Block-based multi-period refresh for energy efficient dynamic memory

Kim

Papaefthymiou²

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

View full text Add to dashboard Cite

Public Reporting burden for this collection of information is estimated to average 1 liour per response, including flie time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and conpleting and reviewing the collection of information. Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302, and DRAMs are widely used In portable applications due to their high storage density. In standby mode their main source of power dissipation Is the refresh operation that periodically restores leaking charge In each cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage.In this paper we Investigate a novel scheme that relies on multiple refresh periods and small refresh blocks to reduce DRAM dissipation by decreasing the number of cells refreshed too often. Long periods are used to accommodate cells with small leakage. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Retention times are further extended by adding a swap cell to each refresh block.We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer Kand a distribution of data retention times, in O(KN^) steps our algorithm computes /< refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a possible implementation of our refresh scheme. In simulations with a 16Mb DRAM, block-based multi-rate refresh reduces standby dissipation by a multiplicative factor of 4 with area overhead below 6%. ABSTRACTDRAMs are widely used in portable applications due to their high storage density. In standby mode, their main source of power dissipation is the refresh operation that periodically restores leaking charge in each cell to its correct level. Conven

show abstract

The evolution of IBM CMOS DRAM technology

Cited by 50 publications

References 36 publications

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques

Contribution of gate induced drain leakage to overall leakage and yield loss in digital submicron VLSI circuits

Block-based multi-period refresh for energy efficient dynamic memory

Contact Info

Product

Resources

About