An adaptive system for protecting a distribution network should determine and implement relay settings that are most appropriate for the prevailing state of the power system. This paper presents a technique for determining cbordinated relay settings. The technique uses the Simplex two-phase method; Phase I determines whether the constraints selected for illustrating the conditionality between primary and back up relays are feasible, and Phase II finds the optimal relay settings. A looped distribution system, protected by directional overcurrent relays, war; used for testing the technique. The tests were conducted in a laboratory environment: some results from those tests are reported in the paper.
As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-µm bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15 • C and by 7 • C in 0.09-µm SOI and bulk CMOS technologies, respectively.
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