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MRAM (magnetic random access memory) technology, based on the use of magnetic tunnel junctions (MTJs) as memory elements, is a potentially fast nonvolatile memory technology with very high write endurance. This paper is an overview of MRAM design considerations. Topics covered include MRAM fundamentals, array architecture, several associated design studies, and scaling challenges. In addition, a 16-Mb MRAM demonstration vehicle is described, and performance results are presented.

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The development of DRAM at IBM produced many novel processes and sophisticated analysis methods. Improvements in lithography and innovative process features reduced the cell size by a factor of 18.8 in the time between the 4Mb and 256Mb generations. The original substrate piate trench cell used in the 4Mb chip is still the basis of the 256Mb technology being developed today. This paper describes some of the more important and interesting innovations introduced in IBM CMOS DRAMs. Among them, shallow-trench isolation, 1-line and deep-UV (DUV) lithography, titanium salicidation, tungsten stud contacts, retrograde n-well, and planarized bacl(-end-ofline (BEOL) technology are core elements of current state-of-the-art logic technology described In other papers in this issue. The DRAM specific features described are borderless contacts, the trench capacitor, trench-isolated cell devices, and the "strap." Finally, the methods for study and control of leakage mechanisms which degrade DRAM retention time are described.^Copyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted witiiout payment of royalty provided tliat (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor.

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Ω−µm 2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15σ(R p ), write threshold spread σ(Vw)/ <7.1%, breakdown-to-write voltage margin over 0.5V, readinduced disturbance rate below 10 -9 , and sufficient write endurance, and is free of unwanted write-induced magnetic reversal. The statistics suggest that a 64Mb chip at the 90-nm node is feasible. IntroductionThe density of STT-RAM [1] can be as competitive with that of embedded DRAM. It is more scalable and consumes less power than the conventional field-MRAM [2]. This paper describes an STT-MRAM with 70x210 nm 2 MTJ devices. This MTJ provides sufficient statistical margins among read-and writeoperation and satisfies the junction long-term reliability requirements.

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