A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

Davarik, B.; Koburger, Charles W.; Schulz, R.; Warnock, J.; Furukawa, Toshio; Jost, Matthias; Taur, Yuan; Schwittek, W.G.; DeBrosse, J.; Kerbaugh, Mike; Mauer, J. L.

doi:10.1109/iedm.1989.74228

Cited by 42 publications

(23 citation statements)

References 4 publications

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“…A schematic cross section of the planarization process sequence is shown in Figure 2. Compared to [4], this planarization sequence has a reduced number of process steps and has replaced the more complex planarization etchback process with an oxide RIE process. At this point, MOS and bipolar devices were fabricated using previously reported processes [3] to evaluate the merit of the proposed structure.…”

Section: Fabricationmentioning

confidence: 98%

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A trench isolation process for BiCMOS circuits

Poon

Lage

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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A new isolation process using 1 pm deep trench is developed for BiCMOS circuits. Well behaved MOSFETs and NPN devices with excellent parasitic performance were achieved. Low leakage diodes with butted junctions were demonstrated by inclusion of an oxidation barrier in the trench liner and utilizing a Ge02 doped oxide with matched thermal coefficient of expansion to the silicon substrate for trench fill. Planarity for arbitrary width isolation was obtained by using oxide RIE followed by chemical-mechanical polishing.

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Section: Fabricationmentioning

confidence: 98%

“…A combination of oxide RIE and chemical mechanical polishing process [4,5] is used for the planarization of arbitrary width trench. A schematic cross section of the planarization process sequence is shown in Figure 2.…”

Section: Fabricationmentioning

confidence: 99%

A trench isolation process for BiCMOS circuits

Poon

Lage

1993

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93

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“…Within the context of the semiconductor industry, CMP was introduced by IBM in the late 1980's as a means to minimize step height and topographical variations resulting from the use of multi-layer metal interconnects in advanced IC designs [2][3][4] . Typical materials used in IC applications include semi-conducting materials such as polysilicon, conducting materials such as aluminum, copper and tungsten and dielectrics, such as silicon dioxide and silicon nitride.…”

Section: Cmp and Ic Applicationsmentioning

confidence: 99%

Chemical mechanical planarization: an effective microfabrication and micromachining technology for MEMS

et al. 2003

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Chemical mechanical planarization (CMP) is an integral process in the semiconductor industry that enables the fabrication of advanced integrated circuit (IC) components. It is the method of choice for obtaining both local and global planarization of IC thin films, including metals, such as copper, aluminum and tungsten, and dielectrics such as silicon dioxide. An emerging area for application of CMP is in Micro-Electro-Mechanical Systems (MEMS). Fabricated from a variety of materials, including polymers, metals and ceramics, MEMS devices present new opportunities and new challenges for CMP. This paper describes the planarization and fabrication requirements of MEMS CMP, from both a materials and a processing perspective, with a comparison to IC CMP. Examples using popular MEMS fabrication materials, such as standard and photosensitive polyimides, alumina and copper, will demonstrate the efffectiveness of CMP for microfabrication and micromachining applications. Additional results will illustrate the use of CMP as a means to selectively and controllably effect a high degree of planarization efficiency on a variety of microelectronics substrates. Finally, the role of CMP in meeting future MEMS/MOEMS-related applications will be addressed.

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“…The amount of this parasitic current depends on the following technological parameters: exact shape of the STI edge, radius of the rounded edge (if rounded), amount of STI recess, etc. Although techniques to reduce this parasitic current by careful design of STI edge have been developed [3]- [5], these are typically employed for the high performance thin gate-oxide device in a digital technology. However, for analog applications and for co-integration of digital and high performance analog technologies for SoC applications often dual or triple gate oxides in a given technology need to be incorporated.…”

Section: Introductionmentioning

confidence: 99%

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Khandelwal

Agarwal

Duarte

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We enhance the capability of industry standard compact model BSIM6 to model the parasitic current I edge at the shallow trench isolation edge. Accurate, efficient, and scalable model for I edge is developed by finding the key differences between I edge and main device drain current (I main ). It is found that I edge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to I main . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

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A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

Cited by 42 publications

References 4 publications

A trench isolation process for BiCMOS circuits

A trench isolation process for BiCMOS circuits

Chemical mechanical planarization: an effective microfabrication and micromachining technology for MEMS

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

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