A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

DeBrosse, J.; Gogl, D.; Bette, Ann-Christin; Hoenigschmid, H.; Robertazzi, R. P.; Arndt, Christine; Braun, Daniel; Casarotto, D.; Havreluk, R.; Lammers, S.; Obermaier, W.; Reohr, W.; Viehmann, H.; Gallagher, W. J.; Müller, Georg

doi:10.1109/jssc.2004.825251

Cited by 58 publications

(18 citation statements)

References 3 publications

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“…The MTJ can be integrated with CMOS using 3-D technology. IBM demonstrated a 128 kb MTJ-based MRAM in 2003, showing that MRAM performance can be better than that of DRAMs [59]. In this work, the MTJ security is discussed in Section 6.4.…”

Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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“…This also explains recent results on fast write operation obtained on a MRAM prototype. 19 In the mentioned work the MRAM prototype was especially optimized for fast pulse propagation. Nevertheless, a strong increase of the write error rate was observed for write field application times shorter than 1.5 ns.…”

Section: Bit Addressing: Precessional Switching Under Easy Axis Bmentioning

confidence: 99%

Effective bit addressing times for precessional switching of magnetic memory cells

Schumacher

Chappert

Sousa

et al. 2005

Journal of Applied Physics

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We study the effective reversal times for bit-addressed precessional switching of the magnetization in magnetic random access memories (MRAMs). In our experiments the ultrafast magnetization dynamics of the free layer of a microscopic magnetic tunnel junction cell is accessed by means of ultrafast magnetotransport. Bit-addressed switching is studied by a fast perpendicular field pulse in combination with an easy axis bias field. For vanishing effective easy axis bias fields ultrafast quasiballistic switching of the magnetization can be achieved. Furthermore the characteristic oscillatory behavior of the precessional switching under variation of the pulse duration is observed. In a certain easy axis bias field range, the so-called addressing windows, the final magnetization state after the fast pulse is always aligned with the bias field which allows reliable bit addressing in a MRAM. Also here fast magnetization switching can be obtained. However, the decay time of the remaining magnetic excitations after bit addressing strongly depends on the initial and final orientations of the magnetization. This variation leads to different effective bit addressing times for switching and nonswitching events which could limit the MRAM operation speed.

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“…The technology requires the addition of three mask layers to a standard CMOS technology for implementation of the MRAM element. This same team also developed a 128Kb embedded MRAM core macro for use in system-on-chip ASICs in 180nm technology [7]. The core demonstrated read access time of 16ns with some bits as fast as 10ns, and write pulses as low as 1.5ns.…”

Section: Enabling Computing Technologiesmentioning

confidence: 99%

Applying Reconfigurable Processing Technologies to Spaceborne Applications

Marshall

Berger

2005

2005 IEEE Aerospace Conference

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Reconfigurability 12 is a key element to extracting the most from any spacecraft or spacecraft subsystem. It allows systems to become more autonomous, maximizes their usage once deployed and delays obsolescence by allowing new uses of the spaceborne asset, often in ways not envisioned by its creators. This paper briefly explores the needs for reconfigurable systems and then presents a four dimension taxonomy to describe their make-up and potential growth areas.It describes recent advances in non-volatile memory, reconfigurable technologies and processors including BAE Systems' chalcogenide, which is the base of an upcoming 4 megabit C-RAM TM device, and after that various C-RAM embedded devices. The BAE Systems reconfigurable architecture is reviewed and potential near term products described. Finally, the types of, and challenges using new technologies in reconfigurable systems are described. This includes discussing the need to standardize the interfaces in order to allow a growth similar to what has occurred in spacecraft processors.

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A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

Cited by 58 publications

References 3 publications

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

Effective bit addressing times for precessional switching of magnetic memory cells

Applying Reconfigurable Processing Technologies to Spaceborne Applications

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