Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Mandelman, J.; Dennard, R.H.; Bronner, G.; DeBrosse, J.; Divakaruni, R.; Li, Y.; Radens, C.

doi:10.1147/rd.462.0187

Cited by 230 publications

(105 citation statements)

References 37 publications

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“…Increasing the cell density, however, also has a negative impact on memory reliability due to three reasons. First, a small cell can hold only a limited amount of charge, which reduces its noise margin and renders it more vulnerable to data loss [14,47,72]. Second, the close proximity of cells introduces electromagnetic coupling effects between them, causing them to interact with each other in undesirable ways [14,42,47,55].…”

Section: Introductionmentioning

confidence: 99%

“…First, a small cell can hold only a limited amount of charge, which reduces its noise margin and renders it more vulnerable to data loss [14,47,72]. Second, the close proximity of cells introduces electromagnetic coupling effects between them, causing them to interact with each other in undesirable ways [14,42,47,55]. Third, higher variation in process technology increases the number of outlier cells that are exceptionally susceptible to inter-cell crosstalk, exacerbating the two effects described above.…”

Section: Introductionmentioning

confidence: 99%

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Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

435

1,019

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Abstract. Memory isolation is a key property of a reliable and secure computing system -an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

435

1,019

View full text Add to dashboard Cite

show abstract

“…On the technology front, two key trends profoundly affect memory systems. First, there is increasing difficulty scaling the well-established chargebased memory technologies, such as DRAM [47,4,37,1] and flash memory [34,46,9,10,11], to smaller technology nodes. Such scaling has enabled memory systems with reasonable capacity and efficiency; lack of it will make it difficult to achieve high capacity and efficiency at low cost.…”

Section: Trends and Requirementsmentioning

confidence: 99%

Memory scaling: A systems architecture perspective

Mutlu

2013

2013 5th IEEE International Memory Workshop

217

207

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Abstract-The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques.In this paper, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we survey three key solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system, 2) designing a memory system that employs emerging memory technologies and takes advantage of multiple different technologies, 3) providing predictable performance and QoS to applications sharing the memory system. We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.

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“…Satisfying such a demand with DRAM alone may prove difficult due to DRAM scaling challenges [9]. To address this problem, recent work has proposed using DRAM as a cache to large non-volatile memories, such as phase-change memory (PCM), which are projected to be much more scalable than DRAM at comparable access latencies [6].…”

Section: Introductionmentioning

confidence: 99%

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Meza

Chang

Yoon

et al. 2012

IEEE Comput. Arch. Lett.

150

114

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Abstract-Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

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Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Cited by 230 publications

References 37 publications

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Memory scaling: A systems architecture perspective

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

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