Reactive ion etching of thin gold films using chlorine false(Cl2false) , carbon tetrafluoride false(CF4false) , carbon tetrachloride false(CCl4false) , and a mixture of these gases was investigated. Etch rates were studied by changing the etching gas composition, pressure, and power in a parallel‐plate reactive ion etcher. Reactive ion etching of gold using Cl2 or CCl4 yields a low etch rate and a carbon residue formation on etched surfaces. The introduction of CF4 to the Cl2 did not improve the etch rate. However, the addition of CF4 to CCl4 was found to etch the carbon residue and significantly enhance the etch rate of gold. The etch rate of gold varies from 30 Å/min using a chlorine plasma to 990 Å/min using a mixture of CF4 and CCl4 . For a mixture of CF4 and CCl4 , the etch rate of gold was found to be twice the etch rate of positive photoresist, suggesting that positive photoresist is a practical mask for most applications involving the reactive ion etching of thin gold films.
Etching in semiconductor processing typically involves using halides because of the relatively fast rates. Bromine-containing plasmas can generate high aspect ratio trenches, desirable for dynamic random access memory and microelectromechanical system applications, with relatively straight sidewalls. We present scanning electron microscope images for silicon-etched trenches in a HBr plasma. Using a feature profile simulation, we show that the removal yield parameter, or number of neutrals removed per incident ion due to all processes (sputtering, spontaneous desorption, etc.), dictates the profile shape. We find that the profile becomes pinched off when the removal yield is a constant, with a maximum aspect ratio (AR) of about 5 to 1 (depth to height). When the removal yield decreases with increasing ion angle, the etch rate increases at the corners and the trench bottom broadens. The profiles have ARs of over 9:1 for yields that vary with ion angle. To match the experimentally observed etched time of 250 s for an AR of 9:1 with a trench width of 0.135 μm, we find that the neutral flux must be 3.336×1017 cm2 s−1.
Small ground rule ͑Ͻ0.175 m͒, high aspect ratio ͑feature size to depth ratio Ͼ40͒ trenches in silicon are necessary to achieve required values of cell capacitance in the fabrication of charge-storage capacitors in dynamic random access memory devices. Etching of trenches suffers from a dynamic reactive ion etching ͑RIE͒ lag mechanism caused by constriction of trench openings during the etch process. Also, at high aspect ratios ͑accentuated by constriction of trench openings͒, reduced ion energy and etchant species flux to the trench bottom ͑etch front͒ results in slower etch rates leading to etch stop. This dynamic RIE lag effect and potential etch stop pose significant challenges towards obtaining deeper trenches. In this paper, two methods are proposed to minimize these problems. Short duration cleaning steps, predominantly etching in nature without any builtin deposition component, are used intermittently during the multistep etching sequence. Mask selectivity is preserved as these cleaning steps do not contribute significantly to the mask etch rate. The first method decreases the constriction of the trench opening by thinning the sidewall deposition, thus partially restoring the design dimension of the trench opening. The second method removes the etch-stop or blocking layer at the bottom of the trench without significantly contributing to sidewall thinning. These methods increase the differential etch rate of silicon at high aspect ratios, thereby help achieve the higher silicon depths required to meet the manufacturing process tool utilization targets.
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