Etching in semiconductor processing typically involves using halides because of the relatively fast rates. Bromine-containing plasmas can generate high aspect ratio trenches, desirable for dynamic random access memory and microelectromechanical system applications, with relatively straight sidewalls. We present scanning electron microscope images for silicon-etched trenches in a HBr plasma. Using a feature profile simulation, we show that the removal yield parameter, or number of neutrals removed per incident ion due to all processes (sputtering, spontaneous desorption, etc.), dictates the profile shape. We find that the profile becomes pinched off when the removal yield is a constant, with a maximum aspect ratio (AR) of about 5 to 1 (depth to height). When the removal yield decreases with increasing ion angle, the etch rate increases at the corners and the trench bottom broadens. The profiles have ARs of over 9:1 for yields that vary with ion angle. To match the experimentally observed etched time of 250 s for an AR of 9:1 with a trench width of 0.135 μm, we find that the neutral flux must be 3.336×1017 cm2 s−1.
Small ground rule ͑Ͻ0.175 m͒, high aspect ratio ͑feature size to depth ratio Ͼ40͒ trenches in silicon are necessary to achieve required values of cell capacitance in the fabrication of charge-storage capacitors in dynamic random access memory devices. Etching of trenches suffers from a dynamic reactive ion etching ͑RIE͒ lag mechanism caused by constriction of trench openings during the etch process. Also, at high aspect ratios ͑accentuated by constriction of trench openings͒, reduced ion energy and etchant species flux to the trench bottom ͑etch front͒ results in slower etch rates leading to etch stop. This dynamic RIE lag effect and potential etch stop pose significant challenges towards obtaining deeper trenches. In this paper, two methods are proposed to minimize these problems. Short duration cleaning steps, predominantly etching in nature without any builtin deposition component, are used intermittently during the multistep etching sequence. Mask selectivity is preserved as these cleaning steps do not contribute significantly to the mask etch rate. The first method decreases the constriction of the trench opening by thinning the sidewall deposition, thus partially restoring the design dimension of the trench opening. The second method removes the etch-stop or blocking layer at the bottom of the trench without significantly contributing to sidewall thinning. These methods increase the differential etch rate of silicon at high aspect ratios, thereby help achieve the higher silicon depths required to meet the manufacturing process tool utilization targets.
During the last quarter century or so, plasma processing has become a critical industrial technology for the development and manufacture of semiconductor devices. Gaseous plasmas have been used for sputter and chemical vapor deposition of thin films, pattern transfer in mask fabrication, etching of thin films, resist stripping, surface modification and as an ion source in ion implantation. It is the most pervasive technology in the manufacture of silicon-based integrated circuits.
The planarization and recessing of polysilicon to form a plug are processes of increasing importance in silicon IC fabrication. While this technology has been developed and applied to DRAM technology using Trench Storage Capacitors, the need for such processes in other IC applications (i.e. polysilicon studs) has increased. Both planarization and recess processes usually have stringent requirements on etch rate, recess uniformity, and selectivity to underlying films. Additionally, both processes generally must be isotropic, yet must not expand any seams that might be present in the polysilicon fill. These processes should also be insensitive to changes in exposed silicon area (pattern factor) on the wafer. A SF6 plasma process in a polysilicon DPS (Decoupled Plasma Source) reactor has demonstrated the capability of achieving the above process requirements for both plananzation and recess etch. The SF6 process in the decoupled plasma source reactor exhibited less sensitivity to pattern factor than in other types of reactors. Control of these planarization and recess processes requires two endpoint systems to work sequentially in the same recipe: one for monitoring the endpoint when blanket polysilicon (100% Si loading) is being planarized and one for monitoring the recess depth while the plug is being recessed (<10% Si loading). The planarization process employs an optical emission endpoint system (OES). An interferometric endpoint system (IEP), capable ofmomtonng lateral interference, is used for detennining the recess depth. The ability ofusing either or both systems is required to make these plug processes manufacturable. Measuring the recess depth resulting from the recess process can be difficult, costly and time-consuming. An Atomic Force Microscope (AFM) can greatly alleviate these problems and can serve as a critical tool in the development of recess processes.
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