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The Fermi level at the Ga oxide/GaAs interface has been unpinned by rf plasma cleaning the GaAs surface in H2 and N2. Following plasma cleaning, a Ga oxide film is reactively electron beam deposited onto the substrate. Metal-oxide-semiconductor (MOS) capacitors fabricated on these structures show good high-frequency capacitance-voltage characteristics. This indicates that the density of interface states has been reduced to ∼1011 eV−1 cm−2. The MOS capacitors are found to be stable in air after several months.

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An "index alignment" method, based on the registration of fiducial marks, was previously developed for passive alignment of a laser array to a corresponding fiber array. This method has recently been improved and used to fabricate laserfiber array transmitter modules for single-mode operation at 1300 nm.An improved computer-controlled alignment-stage system with machine-vision features has been installed in order to render the alignment procedure faster, more precise, and more reliable; this system was particularly effective in quick achievement of the difficult but necessary angular alignment of the components. Special "self-registration" component-fabrication techniques were also developed to avoid mask-registration errors associated with the fabrication of the laser chip and the fiber carrier. Measures were also taken to improve the accuracy of alignment of the etch mask to the silicon crystallographic axes during fiber-carrier fabrication, and to improve the etch-stop indication process.Test results showed that for single-mode operation at 1300 nm, coupling efficiencies greater than 8% could be achieved, approaching the 9% coupling efficiency observed with active alignment. Tests of a completed module at 1 Gb/s showed values of RIN low enough to permit operation at distances of about 1 km.

GaAs metal-semiconductor field-effect transistors (MESFETs) and other integrated-circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self-aligned, refractory-gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni-Au-Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni-Au wiring. On-water threshold voltage standard deviations as low as 31 mV for 1-μm E-FETs and 49 mV for 1-μm D-FETs were measured using 51-mm standard semi-insulating liquid-encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self-aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square-law coefficient, subthreshold leakage, gate capacitance, backgating, contact resistance, and wiring and insulation characteristics were also measured and found satisfactory. Fully functional 1-μm gate E/D MESFET circuits including a 4×4 bit multiplier, a 4×4 crosspoint switch, a 448-bit static RAM, and an integrated photodiode amplifier were demonstrated.