Plasma-etching processes for ULSI semiconductor circuits

Armacost, M.; Hoh, P.D.; Wise, Rich; Yan, Weirong; Brown, J.J.; Keller, John H.; Kaplita, G. A.; Halle, Scott; Müller, K.P.; Naeem, M.; Srinivasan, Sunil; Ng, H.; Gutsche, M.; Gutmann, A.; Spuler, B.

doi:10.1147/rd.431.0039

Cited by 50 publications

(26 citation statements)

References 34 publications

(52 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…At the very the top of the trench the field accelerates the ions downward, but it quickly changes direction towards the bottom. The reduction in the device size and multilayer structures requires a high-aspect ratio AR (the ratio between the height and width of the trench) in the SiO 2 etching [57][58][59]. With increasing the aspect ratio, the charging effects becomes more profound.…”

Section: Charging Effectsmentioning

confidence: 99%

Top down nano technologies in surface modification of materials

Radjenović

Radmilović-Radjenović

2011

Open Physics

View full text Add to dashboard Cite

Abstract:This article contains a broad overview of etch process as one of the most important top-down technologies widely used in semiconductor manufacturing and surface modification of nanostructures. In plasma etching process, the complexity comes from the introduction of new materials and from the constant reduction in dimensions of the structures in microelectronics. The emphasis was made on two types of etching processes: dry etching and wet etching illustrated by three dimensional (3D) simulation results for the etching profile evolution based on the level set method. The etching of low-k dielectrics has been demonstrated via modelling the porous materials. Finally, simulation results for the roughness formation during isotropic etching of nanocomposite materials as well as smoothing of the homogeneous materials have also been shown and analyzed. Simulation results, presented here, indicate that with shrinking microelectronic devices, plasma and wet etching interpretative and predictive modeling and simulation have become increasingly more attractive as a tool for design, control and optimization of plasma reactors. PACS (2008):81.05. Rm, 85.40.Hp, 85.85.+j, 87.10.Ed

show abstract

Section: Charging Effectsmentioning

confidence: 99%

Top down nano technologies in surface modification of materials

Radjenović

Radmilović-Radjenović

2011

Open Physics

View full text Add to dashboard Cite

show abstract

“…For the polysilicon etch step, HBr/O 2 chemistry is typically used [25]. During this step, a bromine rich oxide-like passivation film forms on the sidewall and on the bottom of the space between the gate lines.…”

Section: Impact Of Resist Etch and Poly-silicon Etch Processes On Swamentioning

confidence: 99%

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

et al. 2008

View full text Add to dashboard Cite

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

show abstract

“…The reduction in the device size and multilayer structures requires a high-aspect ratio (height/width of the trench, AR) in the SiO 2 etching [61]- [63]. As the aspect ratio increases, the charging effects becomes more profound.…”

Section: Charging Effectsmentioning

confidence: 99%

Top down nano technologies in production of integrated circuits and surface modification of materials

Petrović

Radjenović

Radmilović-Radjenović

2008

2008 26th International Conference on Microelectronics

View full text Add to dashboard Cite

As microelectronic devices continue to shrink and process requirements become ever more stringent, plasma modeling and simulation becomes increasingly more attractive as a tool for design, control and optimization of plasma reactors. Nowadays, plasmaetching processes are expected to produce patterns from the nanometer to the micrometer range. Charging effects in the etching of dielectrics due to ions accumulation in the shallow trenches or contact hole cause damage such as notching and earlier etching stop. In this article, a brief overview of the plasma etch process with emphasis on charging induced damage has been made. In addition, a level set method was applied to the 3D simulation of the etching profile of high aspect ratio trenches into silicon. Calculations were performed in the case of simplified model of Ar + /CF 4 non-equilibrium plasma etching of SiO 2 . The time dependence of the profile charging as well as charging on profile during SiO 2 etching in plasma are presented. We shall also illustrate the properties of etching of organic low-k dielectrics.

show abstract

Plasma-etching processes for ULSI semiconductor circuits

Cited by 50 publications

References 34 publications

Top down nano technologies in surface modification of materials

Top down nano technologies in surface modification of materials

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

Top down nano technologies in production of integrated circuits and surface modification of materials

Contact Info

Product

Resources

About