Advanced profile control and the impact of sidewall angle at gate etch for critical nodes

Abstract

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

Systematic procedure to optimize chamber seasoning conditions with optical emission spectroscopy in plasma etching

“…(3) is obtained, an optimization problem with constraints can be solved with a quadratic objective function described in Eq. (4) in order to obtain optimum MVs in MIMO control [12][13][14][15] J ¼ min…”

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

“…3 Fig. 16,19 Consequently, on the top of the PR, a corner attack can be enhanced by neutral fluxes because there are more neutral radicals at the top than at the bottom of the PR. This will be a very critical step for subsequent etches because it defines the CD and affects the final LWR.…”

Optimizing integrated optical CD monitoring by floating pre-process variations in a complex multi-layer structure

“…The integration of metrology tools into the process tools such as litho track allows measurements to take place right after the resist development while other wafers in the lot are under processing, and therefore a faster send back to address any possible process drift is made possible. In fact, these measurements can be applied to both litho and etch processes [1][2][3][4][5][6][7][8][9], allowing a full scope of APC (advanced process control) for best benefit of overall process tuning. Besides, IM also provides benefits such as high throughput enabling for more sampling of lots, resist side wall angle making allowing process engineers for wider scope of understanding of the litho cell parameter control, and non-destructive characteristics to ensure repeatable and reliable measurement.…”