This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50nm trench pattern, which are lower resistance than Al and good reliabilities.
Environmentally benign etching process of amorphous silicon and tungsten using species evaporated from polytetrafluoroethylene and fluorinated ethylene propylene As chamber conditions gradually change with wafer processing, periodic wet cleaning is an inevitable event in semiconductor manufacturing. Since the chamber conditions are initialized during the wet cleaning, a chamber conditioning process called chamber seasoning follows the wet cleaning step. In this paper, a systematic procedure to optimize chamber seasoning for plasma etching is proposed, and the effectiveness is demonstrated in a semiconductor manufacturing environment. In order to quantitatively analyze plasma conditions for chamber seasoning and to achieve the optimum conditions objectively, a normalization technique for optical emission spectroscopy called a selfbackground normalization technique and a computational optimization process is suggested. By applying the optimized chamber seasoning conditions, a plasma reactor which is suffering from a serious etch rate drift after wet cleaning returns to a production ready status. Also, the etch rate of Si, which is an index for production readiness, is perfectly matched to 37.8 A/s for production. Hopefully, the proposed methodology in this paper will be disseminated to semiconductor manufacturers who experience similar issues after wet cleaning.
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