A high reliability metal insulator metal capacitor for 0.18 μm copper technology

Armacost, M.; Augustin, A.; Felsner, P.; Feng, Y.; Friese, G.; Heidenreich, J.; Hueckel, G.; Prigge, O.; Stein, K.

doi:10.1109/iedm.2000.904282

Cited by 38 publications

(22 citation statements)

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“…The excellent electrical performance of MIM capacitors with SiO 2 and Si 3 N 4 as dielectrics has been successfully demonstrated in Al and Cu back-end-of-line (BEOL) process. [5][6][7] However, the capacitance densities are low (usually below 2 fF lm -2 ). Further reducing the dielectric thicknesses of SiO 2 and Si 3 N 4 can increase the capacitance density, but the increase may be offset by poorer leakage current, breakdown voltage, and voltage linearity.…”

Section: Introductionmentioning

confidence: 98%

Atomic Layer Deposited High‐κ Films and Their Role in Metal‐Insulator‐Metal Capacitors for Si RF/Analog Integrated Circuit Applications

Zhu

Cho

2006

Chemical Vapor Deposition

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In this paper, we present an extensive evaluation of metal-insulator-metal (MIM) capacitors by comparing various high-j dielectric structures based on atomic layer deposited HfO 2 and Al 2 O 3 films at two thicknesses. The results indicate that laminate-structured MIM capacitors provide superior performance to their sandwiched/stacked counterparts in both thin (∼13 nm) and thick (∼55 nm) dielectric films. Benefits include low leakage current, good polarity-independent electrical characteristics, high-breakdown electrical field (voltage), and long time-to-breakdown while maintaining comparable capacitance density and voltage coefficients of capacitance. It is noted, however, that the benefits of the laminate structure become less significant when the dielectric thickness decreases. The advantages of the laminate structure are mainly attributed to the alternate insertions of Al 2 O 3 into bulk HfO 2 , thereby preventing crystallization of HfO 2 .

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Section: Introductionmentioning

confidence: 98%

Atomic Layer Deposited High‐κ Films and Their Role in Metal‐Insulator‐Metal Capacitors for Si RF/Analog Integrated Circuit Applications

Zhu

Cho

2006

Chemical Vapor Deposition

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“…The use of MIM capacitors in these applications has attracted great attention because of their highly conducting electrodes and low parasitic capacitances [21,22,23]. A high capacitance density is required for a MIM capacitor to allow for small area, to increase the circuit density, and to further reduce the manufacturing costs.…”

Section: Materials Science Forummentioning

confidence: 99%

High-K: Latest Developments and Perspectives

Bauer

Lemberger

Erlbacher

et al. 2008

MSF

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Abstract. The paper reviews recent progress and current challenges in implementing high-k dielectrics in microelectronics. Logic devices, non-volatile-memories, DRAMs and low power mixedsignal components are found to be the technologies where high-k dielectrics are implemented or will be introduced soon. Two gate architectures have to be considerd: MOS with metal as gate electrode and MIM. In particular, Hf-silicates for logic and NVM devices in conventional MOS architecture and ZrO 2 for DRAM cells in MIM architecture are discussed. Fields of applicationsThe breakthrough and thus the enormous growth of the microelectronics, especially in the Information Technology, in the past few decades is based, to a large extend, on the SiO 2 /Si system which was therefore called "a simple gift of nature". Gate dielectrics consisting of ultra thin silicon dioxide layers are the key element in conventional silicon based microelectronic devices. In the very beginning of the microelectronics, the thickness of the SiO 2 gate oxide was a few hundred nanometers. Nowadays, state-of-the-art MOSFETs (metal oxide semiconductor field effect transistor) require gate oxide thicknesses of just a few atomic layers. Until recently, the continuous scaling of the ULSI (ultra large scale integration) devices has been accomplished by shrinking physical dimensions. Physical gate oxides with physical thicknesses in the range of 1.6 nm are currently fabricated and thicknesses below 1.0 nm will be requested for future device generations [1]. In this thickness range, key dielectric parameters degrade, like gate leakage current, channel mobility, reliability etc. [2,3,4]. Thus, the necessity arises to replace the SiO 2 with a dielectric of higher permittivity [5,6]. Application of oxides with a higher dielectric constant (high-k) allows for a physically thicker insulating layer with the same capacitance per unit area as that required for SiO 2 . The so-called equivalent oxide thickness (EOT) is defined as follows: EOT = d high-k · k SiO2 / k high-k .(1) d high-k is the physical oxide thickness, k SiO2 and k high-k are the dielectric constant of the silicon dioxide and the high-k oxide, respectively. But, the high-k dielectric has to satisfy several requirements to fulfil all the demands of state-of-the-art gate dielectrics. First, it has to be thermodynamically stable in contact with silicon [7], it must be process compatible with CMOS (complementary MOS) and withstand source/drain implant annealing, oxygen diffusion should be low to prevent generation of a sizeable SiO 2 interface layer (IL) or trapping defects [8], and it must have sufficiently high band offsets to act as barrier for electrons and holes [9]. Also, the high-k oxide has to show a high quality interface to silicon, with only few interface or defect states within the silicon band gap, be- Online: 2008-03-24 ISSN: 1662-9752, Vols. 573-574, pp 165-180 doi:10.4028/www.scientific.net/MSF.573-574.165 © 2008 This is an open access article under the CC-BY 4.0 license (https://creativecomm...

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“…14,15,3 A similar compensating feature is expected in the case of temperature coefficient of capacitance (TCC), since STO possesses a positive value 16 whereas SiO 2 has a negative value. 17 In this work SAS dielectric stacks of different thicknesses with a monolayer of Al 2 O 3 sandwiched between SSTO layers were investigated to achieve better performing MIM In all the capacitors the capacitance density was found to vary in a fairly linear manner with respect to temperature (Class 1). 19 The temperature coefficient of capacitance T  , a figure of merit of the dielectric capacitor devices, is formulated as: Another contributing influence might be the effect of fewer charge traps at the interface; these cannot follow the signal at higher frequencies.…”

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confidence: 99%

Si:SrTiO3-Al2O3-Si:SrTiO3 multi-dielectric architecture for metal-insulator-metal capacitor applications

Dugu

Pavunny

Scott

et al. 2016

Applied Physics Letters

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A high reliability metal insulator metal capacitor for 0.18 μm copper technology

Cited by 38 publications

References 1 publication

Atomic Layer Deposited High‐κ Films and Their Role in Metal‐Insulator‐Metal Capacitors for Si RF/Analog Integrated Circuit Applications

Atomic Layer Deposited High‐κ Films and Their Role in Metal‐Insulator‐Metal Capacitors for Si RF/Analog Integrated Circuit Applications

High-K: Latest Developments and Perspectives

Si:SrTiO3-Al2O3-Si:SrTiO3 multi-dielectric architecture for metal-insulator-metal capacitor applications

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