Planarization of ULSI Topography over Variable Pattern Densities

Abstract

Resist etch-back SiO2 planarization involving a pattern density compensation mask is described for line-space patterns of various dimensions extending to half-micron feature sizes. An empirical model is used to describe the positional dependence of planarization film thickness upon feature density within an array pattern. Design considerations related to the usage of the planarization "block mask" are discussed, a suitable etch condition is specified, and the planarization etchback method is used to achieve long-range, or global planarization.

Semi-empirical modelling of SiO/sub 2/ chemical-mechanical polishing planarization

“…Improving upon traditional planarization methods such as SOG and etchback translates to extending the lateral dimensions at which a method planarizes from 1 to 100 pm to above 1 mm. Currently, without using a mask level, chemical-mechanical polishing (CMP) is the only method available that planarizes effectively at these dimensions [ 1,2,3,4]. For this reason, CMP has become an important technology for interlevel dielectric [3,5] and shallow trench isolation [ 11 planarization.…”

Complete Analytical Solutions of Film Planarization during Spin Coating

“…A quick and easy way to get the degree of planarization (DOP) could be a useful tool for designers and researchers. A few analytical solutions, [1][2][3] numerical solutions, [4][5][6][7][8] empirical models, [9][10][11][12][13][14][15][16] and experimental works 4,5,7,17 already exist. This paper is the first to present the complete analytical solutions of DOP for an isolated feature and periodic features in the whole range of ⍀ 2 .…”

“…[9][10][11][12] The model necessitates the experimental determination of two constants to estimate the film planarization on topography. An empirical model called "average height model" was presented by Wilson and Piacente 13,14 and used by Daubenspeck et al 15 to describe the local planarization. Schiltz 16 proposed an empirical model to calculate the degree of planarization over isolated and periodic ridges.…”

Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

“…Sacrificial Etchback (SE) presents yet another popular method for planarization.[221. [229][230] TTjis planarization technique is based on the fact that the resist materials are better planarize than the insulator layers themselves. Therefore, after a thick coating of insulator film is deposited; the resist material is spun on top of the deposited insulator.…”

“…Utilizing multiple resist layers reduces or eliminates most problems associated with this method and provide "a perfect planarization" [229] procedure. [229][230] pjg A. 13.…”