We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.
Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal-oxide-semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).
We report the electrical characteristics of chemical vapor deposited (CVD) monolayer molybdenum disulfide (MoS2) top-gated field-effect transistors (FETs) on silicon nitride (Si3N4) substrates. We show that Si3N4 substrates offer comparable electrical performance to thermally grown SiO2 substrates for MoS2 FETs, offering an attractive passivating substrate for transition-metal dichalcogenides (TMD) with a smooth surface morphology. Single-crystal MoS2 grains are grown via vapor transport process using solid precursors directly on low pressure CVD Si3N4, eliminating the need for transfer processes which degrade electrical performance. Monolayer top-gated MoS2 FETs with Al2O3 gate dielectric on Si3N4 achieve a room temperature mobility of 24 cm2/V s with Ion/Ioff current ratios exceeding 107. Using HfO2 as a gate dielectric, monolayer top-gated CVD MoS2 FETs on Si3N4 achieve current densities of 55 μA/μm and a transconductance of 6.12 μS/μm at Vtg of −5 V and Vds of 2 V. We observe an increase in mobility at lower temperatures, indicating phonon scattering may dominate over charged impurity scattering in our devices. Our results show that Si3N4 is an attractive alternative to thermally grown SiO2 substrate for TMD FETs.
r e b i b . The devices fabricated for this study used undoped channel Perlectly self aligned Vertical Multiple Independent Gate Field regions and doped polpilimn gates forming depletion mode transistors. Effect Transistor (MiGFET) CMOS devices have been Since the polpilimn and sourddrain regions have similar heights a single fabricated. The unique process used to fabricate these devices implant was optimized for the polpilicon gate, extension a d sourcadrain allow them to been integrated with FinFET devices. Device and regions. The devices still have very good short channel and current circuit simulations have been used to explain the device and capability due to the double gate architecture. A copper backend process explore new applications using this device. A Novel application was used to make ccntact to the two gates, source and drain. of the MIGFET as a signal mixer has been demonstrated. The Electrical Measurement and Devlce Simulation undoped channel, very thin body, perfectly matched gates allow3 (Figures 2ac) shows the electrical characteristics of the NMOS MIGFET. charge coupling of the two signals and provide a new family of When both gates are under the Same bias, the device shows double applications using the MIGFET mixer. Since the process allows gated depletion mode characteristics (Figure 2a). In this mode the device integration of regular CMOS Double gate devicas and MIGFET has all the advantages of a normal FinFET like structure it has extremely devices this technology has potential for various Digital and low leakage, DlBL and close to 6 5 m V . d~ SS. Independently biasing the Analog Mixed-Signal applications. gates of the device the threshold voltage, gain and sub-threshold swing INTRODUCTION are modulated (Figure 2 b.c). The devices show good drive and short MOSFET technologies using gates on more than one side of a channel characteristics for the case when the gates are tied together. A thin channel have shown better short channel characteristics Similar behavior is demonstrated for PMOS MIGFET devices Figure (3e and are proposed as a replacement to planar devices [I-2). c). The sub-threshold swing degradation (Figure 48) and gain (Gm) These fin type devices have a single gate wrap around multiple sensitivity (Figure 4b.c) to second gate bias demonstrate Utat this device silicon surfaces. These devices offer excellent characteristics for is extremely useful for certain applications while it will be difficult to use a given bias across the gate. Independent gate electrcdes on for other digital applications where the sub-threshold swing degradation either side of these channels however enable the channel to be substantially degrades performance. separately biased. CMP and planar Double devices have been Simulation of a 2 D cross section (Figure 5 a,b) f u an NMOS under demonstrated to offer independent dwMe gate operations [4].strong negative gate 1 potential shows a parasitic hole inversion forming The use of CMP to Pndpoint over thin fins could make all the which screens the influence of g...
Mono-crystalline silicon single heterojunction solar cells on flexible, ultra-thin (∼25 μm) substrates have been developed based on a kerf-less exfoliation method. Optical and electrical measurements demonstrate maintained structural integrity of these flexible substrates. Among several single heterojunction ∼25 μm thick solar cells fabricated with un-optimized processes, the highest open circuit voltage of 603 mV, short circuit current of 34.4 mA/cm2, and conversion efficiency of 14.9% are achieved separately on three different cells. Preliminary reliability test results that include thermal shock and highly accelerated stress tests are also shown to demonstrate compatibility of this technology for use in photovoltaic modules.
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