A process/physics-based compact model for nonclassical CMOS device and circuit design

Fossum, J.G.; Ge, Lixin; Chiang, Meng-Hsueh; Trivedi, Vishal; Chowdhury, M.M.; Mathew, L.; Workman, G.O.; Nguyen, Bich‐Yen

doi:10.1016/j.sse.2003.12.030

Cited by 94 publications

(41 citation statements)

References 5 publications

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“…the silicon layer) is undoped or lightly doped, the mobility is constant along the channel and both quantum effects and polydepletion effect are neglected. The last assumption is valid for silicon layer thicknesses down to at least 20 nm: For thinner layers, quantum effects start to play a role [3,7], but might actually be considered as a correction to the classical derivation. The schematic diagram of the DG MOSFET investigated in this work is shown in Figure 1.…”

Section: Implicit Modelmentioning

confidence: 99%

Explicit modelling of the double-gate MOSFET with VHDL-AMS

Prégaldiny¹,

Krummenacher

Diagne³

et al. 2006

Int. J. Numer. Model.

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International audienceThis paper presents a new compact model for the undoped, long-channel double-gate (DG) MOSFET under symmetrical operation. In particular, we propose a robust algorithm for computing the mobile charge density as an explicit function of the terminal voltages. It allows to greatly reduce the computation time without losing any accuracy. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behaviour and the accuracy of the model. Finally, we present the VHDL-AMS code of the DG MOSFET model and related simulation results

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Section: Implicit Modelmentioning

confidence: 99%

Explicit modelling of the double-gate MOSFET with VHDL-AMS

Prégaldiny¹,

Krummenacher

Diagne³

et al. 2006

Int. J. Numer. Model.

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“…4(b) shows the I DS vs. V GS characteristics for the device in Table I predicted using TCAD and the Spice3-UFDG model in FinE. Spice3-UFDG [7] is a physics-based compact model that simulates double-gate devices accurately, and shows excellent agreement with our device simulation in weak as well as strong inversion regions. We have employed device simulations using TCAD in FinE for all subsequent results owing to better convergence behavior in TCAD.…”

Section: Simulation Setupmentioning

confidence: 64%

“…We have developed an environment called FinE (Fig. 3), which integrates Sentaurus TCAD [6] and the Spice3-UFDG [7] model into a single framework, thereby enabling designers to perform high-level experiments with ease. Fig.…”

Section: Simulation Setupmentioning

confidence: 99%

Pragmatic design of gated-diode FinFET DRAMs

Bhoj

Jha

2009

2009 IEEE International Conference on Computer Design

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Abstract-Scaling bulk CMOS SRAM technology for onchip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two/three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on high-activity embedded cache applications. They are highly competitive with an SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is toward an era of multi-gate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multi-gate technology.In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated-diodes and extend it to provide quantitative insight into designing Fin gated-diodes, i.e., gated-diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode configuration and identify parameters that are critical to enhancing the retention time and read current in 2T/3T1D FinFET DRAMs. Additionally, we show the superiority of 2T1D FinFET DRAM over 6T FinFET SRAM having pass-gate feedback (6T PGFB) and 2T1D bulk DRAM under the effect of variations using a quasi-Monte Carlo method implemented in FinE, an environment we have developed for double-gate circuit design that integrates Sentaurus TCAD from Synopsys with the Spice3-UFDG double-gate compact model from University of Florida under a single framework. Finally, we present a new tunable threshold gated-diode FinFET amplifier which uses an n-type gated-diode for voltage-boosting, along with a p-type gated-diode for zero-suppression.

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“…Transfer characteristics are presented for various back-gate voltages (V gbs ). The University of Florida double-gate (UFDG) SPICE model [5] was used for 32-nm FinFET simulations. The power supply was fixed at 1 V. Curves corresponding to SG, LP, and IG modes of operation are indicated.…”

Section: Shorted-gate and Independent-gate Finfetsmentioning

confidence: 99%

“…To quantify the delay of the variously oriented transistors, simulations were performed using a double-gate HSPICE model, called BSIM [24], in conjunction with UFDG [5]. source current (I ds ) with drain-to-source voltage (V ds ) for different channel orientations at the 32-nm FinFET technology node.…”

Section: Oriented Finfetsmentioning

confidence: 99%

FinFET Circuit Design

Mishra¹,

Muttreja²,

Jha

2010

Nanoelectronic Circuit Design

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Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be shorted for higher perfomance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. This chapter provides an introduction to various interesting FinFET logic design styles, novel circuit designs, and layout considerations.

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A process/physics-based compact model for nonclassical CMOS device and circuit design

Cited by 94 publications

References 5 publications

Explicit modelling of the double-gate MOSFET with VHDL-AMS

Explicit modelling of the double-gate MOSFET with VHDL-AMS

Pragmatic design of gated-diode FinFET DRAMs

FinFET Circuit Design

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