FinFET Circuit Design

Mishra, Prateek; Muttreja, A.; Jha, Niraj K.

doi:10.1007/978-1-4419-7609-3_2

Cited by 85 publications

(30 citation statements)

References 24 publications

(33 reference statements)

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“…We observe that simple cell-based estimates (as is the state-of-the-art) to assess rule quality can be misleading highlighting the importance of the ChipDRE framework 8 .…”

Section: Resultsmentioning

confidence: 94%

Comprehensive die-level assessment of design rules and layouts

Ghaida

Badr

Gupta

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Co-development of design rules and layout methodologies is the key to successful adoption of a technology. In this work, we propose Chip-level Design Rule Evaluator (ChipDRE), the first framework for systematic evaluation of design rules and their interaction with layouts, performance, margins and yield at the chip scale (as opposed to standard cell-level). A "good chips per wafer" metric is used to unify area, performance, variability and yield. The framework uses a generated virtual standard-cell library coupled with a mix of physical design, semiempirical, and machine-learning-based models to estimate area and delay at the chip level. The result is a unified design-quality estimate that can be computed fast enough to allow using ChipDRE to optimize a large number of complex design rules. For instance, a study of well-to-active spacing rule reveals a non-monotone dependence of rule value to chip area (although the dependence to cell area is monotone) due to delay changes coming from well-proximity effect.

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“…We observe that simple cell-based estimates (as is the state-of-the-art) to assess rule quality can be misleading highlighting the importance of the ChipDRE framework 8 .…”

Section: Resultsmentioning

confidence: 94%

Comprehensive die-level assessment of design rules and layouts

Ghaida

Badr

Gupta

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…FinFET device structure [11] 978-1-4799-3378-5/14/$31.00 ©2014 IEEE Three modes of FinFET operation [12] are generally used which are the Shorted Gate (SG) mode where the front and the back gate are tied together; Low Power (LP) mode where the back gate is negative or positive biased depending on NFET or PFET; and the Independent Gate (IG) mode where different signals are used to drive the front and the back gate. A mix of the SG and the LP modes can be used to develop mixed mode design style [14]. SG mode is used at critical path of the circuit as it has high ON current.…”

Section: Finfet Based Circuit Designmentioning

confidence: 99%

MITH-Dyn: A multi V<inf>th</inf> dynamic logic design style using mixed mode FinFETs

Nair

Vemuri

2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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In FinFETs, the back-gate of the transistor can be biased to control its V th , thereby reducing leakage power at the expense of performance. This paper proposes a novel multi V th dynamic logic design style (MITH-Dyn) which reduces the leakage power without degrading performance. MITH-Dyn has been tested on dynamic circuits of varying design complexity in both domino logic and np zipper logic. We report leakage savings of 90.83%, 89.14% and total power savings of 36.7%, 32.2% for domino circuits and np zipper circuits respectively. MITH-Dyn has also been extended to C 2 FinFET based latches and registers and also to NORA (No Race) FinFET based pipeline circuits. Total power savings of 27.98% and 36.16% was obtained for 2-stage and 4-stage NORA pipeline circuits respectively. We have used the 45nm FinFET model cards from PTM [1] for all the results reported in this paper.

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“…Studying faults that may affect new technologies such as FinFET [47], starts from the definition of predictive models [48] for the technology and requires the development of models for the basic cells (e.g., memory cells, boolean gates, etc.) that need to be analyzed.…”

Section: A Cross-layer Approach For System Reliability Evaluationmentioning

confidence: 99%

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero

Tselonis

Foutris

et al. 2015

Microprocessors and Microsystems

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International audienceAdvanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market

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FinFET Circuit Design

Cited by 85 publications

References 24 publications

Comprehensive die-level assessment of design rules and layouts

Comprehensive die-level assessment of design rules and layouts

MITH-Dyn: A multi V<inf>th</inf> dynamic logic design style using mixed mode FinFETs

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

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