Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Chatzidimitriou

et al. 2019

IEEE Trans. Comput.

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Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete toolchain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.

Section: Software Fault Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems

Chatzidimitriou

et al. 2019

IEEE Trans. Comput.

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“…We consider the SFMs has introduced by Vallero et. al in [7] that translate the effect of a hardware failure model into the software domain (e.g., an SBU translates into a wrong data of an instruction). SFMs represent the link between the hardware and the software layer of a full system stack.…”

Section: Software Components Characterizationmentioning

confidence: 99%

“…Characterizing the SFBs of a software component means providing the probability of observing a behavior in the presence of one or a combination of SFMs. Due to the limited space available in this paper, the reader may refer to [7] for a detailed description of the concept of SFM and for a preliminary taxonomy. Fig.…”

Section: Software Components Characterizationmentioning

confidence: 99%

RIIF-2: Toward the next generation reliability information interchange format

Carlo

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

et al. 2016

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1-This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.

“…Hardware faults may propagate through the hardware (HW) and software (SW) layers of the system stack, reaching the system output, or be masked during this propagation process. Different protection mechanisms can be employed at different layers implementing what is nowadays called cross-layer reliability enhancement [4] [5] [6]. Accurately measuring the impact on system reliability of any change in the technology, circuit, microarchitecture and software is a complex design task, involving design teams from all abstraction layers.…”

Section: Introductionmentioning

confidence: 99%

Cross-layer system reliability assessment framework for hardware faults

2016 IEEE International Test Conference (ITC)

Politano

et al. 2016

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System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.Peer ReviewedPostprint (author's final draft