RIIF-2: Toward the next generation reliability information interchange format

Savino, Alessandro; Carlo, Stefano Di; Vallero, Alessandro; Politano, Gianfranco; Gizopoulos, Dimitris; Evans, Adrian

doi:10.1109/iolts.2016.7604693

Cited by 2 publications

(1 citation statement)

References 12 publications

(10 reference statements)

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“…RIIF originally focused only on hardware. RIIF2 has been proposed to extend the basic concepts of RIIF to also take software considerations into account [27].…”

Section: Related Workmentioning

confidence: 99%

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.

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“…RIIF originally focused only on hardware. RIIF2 has been proposed to extend the basic concepts of RIIF to also take software considerations into account [27].…”

Section: Related Workmentioning

confidence: 99%

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

View full text Add to dashboard Cite

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Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

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RIIF-2: Toward the next generation reliability information interchange format

Cited by 2 publications

References 12 publications

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Towards Multidimensional Verification: Where Functional Meets Non-Functional

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