is, graphene, transition metal dichalcogenides (TMDs), [ 2,3 ] topological insulators, [ 4 ] h-BN [ 5 ] and h-AlN, [ 6 ] as well the recent phosphorene, [ 7 ] silicene, [ 8 ] and germanene [ 9 ] provide the ability to control the channel thickness at atomic level. This characteristic translates into improved gate control over the channel barrier and into reduced short-channel effects, thus paving the way toward ultimate miniaturization and new device concepts. Recently, 2D transition metal dichalcogenides, have proven to be promising candidates for electronics and optoelectronic applications. [10][11][12][13][14][15][16] From a pioneering perspective, the availability of TMDs with different work functions and band structures guarantees a great potential for band gap engineering of heterostructures. These systems are fundamentally different and more fl exible than traditional heterostructures composed of conventional semiconductors. In particular, due to the weak interlayer interaction, a TMD molecular layer grows from the beginning with its own lattice constant forming an interface with reduced amount of defects. The relaxed lattice matching condition permits to combine almost any layered material and create artifi cial heterojunctions with designed band alignment. 2D heterostructures

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We demonstrate the impact of reducing agents for Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) of WS2 from WF6 and H2S precursors. Nanocrystalline WS2 layers with a two-dimensional structure can be obtained at low deposition temperatures (300-450 °C) without using a template or anneal.

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS2 memristor arrays are reported. The MoS2 memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS2 memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS2 layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

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r e b i b . The devices fabricated for this study used undoped channel Perlectly self aligned Vertical Multiple Independent Gate Field regions and doped polpilimn gates forming depletion mode transistors. Effect Transistor (MiGFET) CMOS devices have been Since the polpilimn and sourddrain regions have similar heights a single fabricated. The unique process used to fabricate these devices implant was optimized for the polpilicon gate, extension a d sourcadrain allow them to been integrated with FinFET devices. Device and regions. The devices still have very good short channel and current circuit simulations have been used to explain the device and capability due to the double gate architecture. A copper backend process explore new applications using this device. A Novel application was used to make ccntact to the two gates, source and drain. of the MIGFET as a signal mixer has been demonstrated. The Electrical Measurement and Devlce Simulation undoped channel, very thin body, perfectly matched gates allow3 (Figures 2ac) shows the electrical characteristics of the NMOS MIGFET. charge coupling of the two signals and provide a new family of When both gates are under the Same bias, the device shows double applications using the MIGFET mixer. Since the process allows gated depletion mode characteristics (Figure 2a). In this mode the device integration of regular CMOS Double gate devicas and MIGFET has all the advantages of a normal FinFET like structure it has extremely devices this technology has potential for various Digital and low leakage, DlBL and close to 6 5 m V . d~ SS. Independently biasing the Analog Mixed-Signal applications. gates of the device the threshold voltage, gain and sub-threshold swing INTRODUCTION are modulated (Figure 2 b.c). The devices show good drive and short MOSFET technologies using gates on more than one side of a channel characteristics for the case when the gates are tied together. A thin channel have shown better short channel characteristics Similar behavior is demonstrated for PMOS MIGFET devices Figure (3e and are proposed as a replacement to planar devices [I-2). c). The sub-threshold swing degradation (Figure 48) and gain (Gm) These fin type devices have a single gate wrap around multiple sensitivity (Figure 4b.c) to second gate bias demonstrate Utat this device silicon surfaces. These devices offer excellent characteristics for is extremely useful for certain applications while it will be difficult to use a given bias across the gate. Independent gate electrcdes on for other digital applications where the sub-threshold swing degradation either side of these channels however enable the channel to be substantially degrades performance. separately biased. CMP and planar Double devices have been Simulation of a 2 D cross section (Figure 5 a,b) f u an NMOS under demonstrated to offer independent dwMe gate operations [4].strong negative gate 1 potential shows a parasitic hole inversion forming The use of CMP to Pndpoint over thin fins could make all the which screens the influence of g...