These authors contributed equally to this work.Fully exploiting the silicon photonics platform requires a fundamentally new approach to realize high-performance laser sources that can be integrated directly using wafer-scale fabrication methods. Direct band gap III-V semiconductors allow efficient light generation but the large mismatch in lattice constant, thermal expansion and crystal polarity makes their epitaxial growth directly on silicon extremely complex. Here, using a selective area growth technique in confined regions, we surpass this fundamental limit and demonstrate an optically pumped InP-based distributed feedback (DFB) laser array grown on (001)-Silicon operating at room temperature and suitable for wavelength-division-multiplexing applications. The novel epitaxial technology suppresses threading dislocations and anti-phase boundaries to a less than 20nm thick layer not affecting the device performance. Using an in-plane laser cavity defined by standard top-down lithographic patterning together with a high yield and high uniformity provides scalability and a straightforward path towards cost-effective cointegration with photonic circuits and III-V FINFET logic.The potential of leveraging well-established and high yield manufacturing processes developed initially by the electronics industry has been the main driver fueling the massive research in silicon photonics over 2 the last decade [1][2][3][4][5][6] . From the start of its development though the lack of efficient optical amplifiers and laser sources monolithically integrated with the silicon platform inhibited the widespread adoption in high-volume applications. Solutions relying on flip-chipping prefabricated laser diodes 7,8 or bonding III-V epitaxial material [9][10][11] are now being deployed in commercially available optical interconnects but are less compatible with standard high-volume and low cost manufacturing processes. Approaches focusing on the engineering of group IV materials have achieved optical gain but still require extensive work to reach room temperature lasing at reasonable efficiency [12][13][14] . Therefore, the monolithic integration of direct bandgap III-V semiconductors, well known to be efficient light emitters, with the silicon photonics platform is heavily investigated. However, considerable hurdles need to be overcome. When directly growing III-V semiconductors on silicon substrates, the large lattice mismatch (εInP/Si = 8.06 %), the difference in thermal expansion and the different polarity of the materials result in large densities of crystalline defects including misfit and threading dislocations, twins, stacking faults and anti-phase boundaries, strongly degrading the performance and reducing the lifetime of any device fabricated in the as-grown layers 15 . Several routes to overcome these issues have been proposed. GaP-related materials can be grown on exact (001) silicon substrates with a small lattice mismatch and pulsed laser oscillation around 980 nm up to 120 K 16 has been achieved but shifting the laser...

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Silicon does not emit light efficiently, therefore the integration of other light-emitting materials is highly demanded for silicon photonic integrated circuits. A number of integration approaches have been extensively explored in the past decade. Here, the most recent progress in this field is reviewed, covering the integration approaches of III-V-to-silicon bonding, transfer printing, epitaxial growth and the use of colloidal quantum dots. The basic approaches to create waveguide-coupled on-chip light sources for different application scenarios are discussed, both for silicon and silicon nitride based waveguides. A selection of recent representative device demonstrations is presented, including high speed DFB lasers, ultra-dense comb lasers, short (850nm) and long (2.3μm) wavelength lasers, wide-band LEDs, monolithic O-band lasers and micro-disk lasers operating in the visible. The challenges and opportunities of these approaches are discussed.

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Integrating high electron mobility III−V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III−V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III− V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III− V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III−V materials, a concept has been developed comprising the deposition in "v-grooves" with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these "v-grooves", the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the "vgrooved" trench. This approach offers a promising method of large-scale integration of III−V materials on Si as required for the fabrication of novel logic and photonic devices.

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

In 0.53 Ga 0.47 As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In 0.53 Ga 0.47 As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum E C is assigned to the "localized" states of α 60°misfit dislocations; another broad electron trap with mean activation energies between E C − 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor K T by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at E V + 0.42 ± 0.01 and E V + 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (V Ga/In 3-/2-) and 60°β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects As Ga/In are discussed for n-type In 0.53 Ga 0.47 As.

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage ͑C-V͒ measurements are necessary for GaAs metaloxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al 2 O 3 , GaAs/Gd 2 O 3 , GaAs/HfO 2 , and In 0.15 Ga 0.85 As/Al 2 O 3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.In the past few years a growing interest in passivation of III-V surfaces has emerged again. Several problems exist, nevertheless, with the characterization of these interfaces, leading to some confusion in the literature. These problems have three main causes: First of all, these interfaces present very high densities of interface states, which leads to weak Fermi level pinning and Fermi level pinning behavior at the surfaces, phenomena rarely observed at Si surfaces. 1 Also the interface state distributions are quite different from the "U"-shaped Si interface state distributions. 2 Finally, the relatively larger bandgap of some III-V semiconductors as compared to Si leads to time constants of interface traps well above the usual time constants observed at Si interfaces, creating very long time constant phenomena, not observable with routine capacitance-voltage ͑C-V͒ characterization techniques. 3 A possible solution to all of these problems is the photoluminescence intensity characterization technique, 4 which is a fast measurement technique that has the big advantage of being sensitive to the integral of all interface states present at the III-V surface. Some disadvantages are the relative insensitivity of the technique in the range of 10 13 -10 15 interface states/ cm 2 , a range in which the largest majority of III-V interfaces unfortunately reside, as well as the difficulty to extract energy distributions of interface state densities ͑D it ͒. In this contribution we apply a different technique, the conductance method, 5 and we apply it at different temperatures, which allows the extraction of interface state density over the whole bandgap of GaAs or In 0.15 Ga 0.85 As. First, some general theory is presented, followed by the presentation of experimental measurements on different GaAs and InGaAs metal-oxidesemiconductor ͑MOS͒ capacitor samples with Al 2 O 3 , Gd 2 O 3 , and HfO 2 gate dielectrics. Measurement MethodC-V measurements are made on MOS structures. The band diagram of a typical MOS structure is shown in Fig. 1, where a gate vo...