Capacitance–Voltage Characterization of GaAs–Oxide Interfaces

Abstract

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage ͑C-V͒ measurements are necessary for GaAs metaloxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al 2 O 3 , GaAs/Gd 2 O 3 , GaAs/HfO 2 , and In 0.15 Ga 0.85 As/Al 2 O 3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.In the past few years a growing interest in passivation of III-V surfaces has emerged again. Several problems exist, nevertheless, with the characterization of these interfaces, leading to some confusion in the literature. These problems have three main causes: First of all, these interfaces present very high densities of interface states, which leads to weak Fermi level pinning and Fermi level pinning behavior at the surfaces, phenomena rarely observed at Si surfaces. 1 Also the interface state distributions are quite different from the "U"-shaped Si interface state distributions. 2 Finally, the relatively larger bandgap of some III-V semiconductors as compared to Si leads to time constants of interface traps well above the usual time constants observed at Si interfaces, creating very long time constant phenomena, not observable with routine capacitance-voltage ͑C-V͒ characterization techniques. 3 A possible solution to all of these problems is the photoluminescence intensity characterization technique, 4 which is a fast measurement technique that has the big advantage of being sensitive to the integral of all interface states present at the III-V surface. Some disadvantages are the relative insensitivity of the technique in the range of 10 13 -10 15 interface states/ cm 2 , a range in which the largest majority of III-V interfaces unfortunately reside, as well as the difficulty to extract energy distributions of interface state densities ͑D it ͒. In this contribution we apply a different technique, the conductance method, 5 and we apply it at different temperatures, which allows the extraction of interface state density over the whole bandgap of GaAs or In 0.15 Ga 0.85 As. First, some general theory is presented, followed by the presentation of experimental measurements on different GaAs and InGaAs metal-oxidesemiconductor ͑MOS͒ capacitor samples with Al 2 O 3 , Gd 2 O 3 , and HfO 2 gate dielectrics. Measurement MethodC-V measurements are made on MOS structures. The band diagram of a typical MOS structure is shown in Fig. 1, where a gate vo...

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

“…Energy distributions of D it for the dielectric/GaAs interface were extracted based on the conductance method 9,[40][41][42] from the corresponding C-V and G-V data obtained at various temperatures. Each D it value was calculated assuming 43 where q is the charge of an electron, G p is the parallel conductance estimated from the C-V and G-V data, and ω is the measured pulsation. A high-temperature measurement (150…”

“…A peak loss showing the frequency shift as a function of gate voltage reflects the D it response according to the standard MOS interface theory. 40,43 The peak loss decreased slightly when (111)A substrate was used. In contrast, the constant plateau loss was clearly distinct from the D it peak, and was related to the accumulation dispersion in the C-V curve.…”

Temperature and frequency dependent electrical characterization of HfO2/InxGa1−xAs interfaces using capacitance-voltage and conductance methods

“…[3][4][5] With respect to GaAs, frequency dispersion in the depletion region has been observed by Brammertz et al for devices at temperatures higher than 120°C, which are attributed to mid-gap interface states in GaAs. 18 In quantifying the interface state defect density contributions to the CV and GV responses, the conductance technique, as developed for Si/ SiO 2 systems, is applied here to the Pd/ HfO 2 / In 0.53 Ga 0.47 As/ InP devices. 8,19,20 The technique involves measuring the capacitance and conductance at a constant V gate while applying a logarithmic frequency sweep from 50 Hz to 1 MHz.…”

A Model of Numerical Calculation of Conductivity for III-V MBE Epilayers Using a Hall Device

“…Figures [16][17][18][19] show that the changes in the conductance components of InAs changes are independent of temperature. The main part of the conductance is attributed to the part of the charge carriers.…”

“…An exhaustive review concerning these phenomena was undertaken by Meyer et al [5]. Such disorder was first described and interpreted by the so-called mobility spectrum by Beck and Anderson [6] and many papers have focused on this problem [7][8][9][10][11][12][13][14][15][16][17][18][19][20]. For the proper characterisation of a multicarrier conduction system, the number of independent measurements must match the number of desired physical quantities.…”