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In 0.53 Ga 0.47 As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In 0.53 Ga 0.47 As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum E C is assigned to the "localized" states of α 60°misfit dislocations; another broad electron trap with mean activation energies between E C − 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor K T by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at E V + 0.42 ± 0.01 and E V + 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (V Ga/In 3-/2-) and 60°β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects As Ga/In are discussed for n-type In 0.53 Ga 0.47 As.

We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.

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We investigated the passivation of In0.53Ga0.47As (001) surface by molecular beam epitaxy techniques. After growth of strained In0.53Ga0.47As on InP (001) substrate, HfO2/Al2O3 high-κ oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (Dit) of the Al2O3/In0.53Ga0.47As interface have been revealed by conductance measurement, indicating a downward Dit profile from the energy close to the valence band (medium 1012 cm−2eV−1) towards that close to the conduction band (1011 cm−2eV−1). The low Dit’s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO2 has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO2 thickness (dielectric constant of HfO2 ∼20) and the remained low Dit’s due to the thin Al2O3 passivation layer. The sample with HfO2 (3.4 nm)/Al2O3 (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of ∼0.93 nm.

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InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/lm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.