Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

Alian, A.; Pourghaderi, Mohammad Ali; Mols, Yves; Cantoro, Mirco; Ivanov, Tsvetan; Collaert, N.; Thean, A.

doi:10.1109/iedm.2013.6724644

Cited by 38 publications

(37 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Si-passivation of (Si)Ge channels with SiO2/HfO2 dielectric stack yields superb pMOS reliability (SiGe relaxed-Ge strainedGe, both planar and finFETs) and sufficient nMOS reliability (relaxed-Ge). Alternative gate stacks based on GeOx IL obtained by thermal or plasma oxidation through a thin Al2O3 capping layer [14] yield poor CMOS reliability, similar to InGaAs n-channel devices with Al2O3 gate dielectric [15]. [7,12].…”

Section: Bti In Ge Devicesmentioning

confidence: 99%

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Franco

Kaczer

Roussel

et al. 2014

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW)

View full text Add to dashboard Cite

We present a review of our recent studies of BTI in FET devices fabricated in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies when a Si cap is used to passivate the channel and to fabricate a standard SiO2/HfO2 gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack. We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain engineering) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then invoke the model to understand the excessive BTI in other high-mobility channel gate stacks, as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.

show abstract

Section: Bti In Ge Devicesmentioning

confidence: 99%

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Franco

Kaczer

Roussel

et al. 2014

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW)

View full text Add to dashboard Cite

show abstract

“…Breaking the out of plane covalent bonds increases the dangling bonds on the surface, resulting in mobility degradation due to surface scattering of electrons. 3 In this context, the family of 2D crystals such as graphene and transition metal dichalcogenides (MX 2 ) offer an interesting case to investigate as alternate ultra-thin body channels. The layers being weakly bonded to each other only by Van der Waals forces and no out-of-plane covalent bonds, there are less dangling bonds than in case of thinning down 3D semiconductors.…”

mentioning

confidence: 99%

Insight on the Characterization of MoS₂Based Devices and Requirements for Logic Device Integration

Rosa

Arutchelvan

Radu

et al. 2016

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

MoS 2 based transistors are being explored as a promising candidate for different applications. The techniques employed to characterize these devices have been directly adapted from 3D semiconductors, without considering the validity of the assumptions. In this work, we discuss the limitations of two-probe (2P), four probe (4P) and transfer length methods (TLM) for extracting electrical parameters. Based on finite-element modeling, we provide design considerations for 4P structures to measure more accurately. Extracting the parameters from these techniques in the appropriate regimes, we identify contact resistance R C to be critical for scaled MoS 2 devices. Using 4P and TLM measurements along with temperature dependent measurements, we derive further insights into the behavior of the R C in the subthreshold and linear regime. Additionally, we propose an empirical model for the on-state contact resistance. The ever-growing demand in semiconductor industry for faster, denser, efficient and robust technology has been driving the need for innovative solutions. Though, scaling was very effective in this regard, in recent years there are growing challenges for the conventional three-dimensional (3D) semiconductors.1 One limitation is the reduced electrostatic control of the gate over the device channel as the channel length (L CH ) get smaller. To overcome this problem multigate technologies evolved and FINFET structures has become the de facto standard for high performance devices. However, even these devices face problems due to, among other things, the 3D nature of these devices.2 Another possible solution is to use 2D planar technologies with ultra-thin body semiconductors to allow for better electrostatic control without losing the two-dimensional (2D) nature of the processing and the device. Nevertheless, this cannot be achieved with conventional 3D semiconductors due to performance degradation on thinning below 100 nm. Breaking the out of plane covalent bonds increases the dangling bonds on the surface, resulting in mobility degradation due to surface scattering of electrons. 3In this context, the family of 2D crystals such as graphene and transition metal dichalcogenides (MX 2 ) offer an interesting case to investigate as alternate ultra-thin body channels. The layers being weakly bonded to each other only by Van der Waals forces and no out-of-plane covalent bonds, there are less dangling bonds than in case of thinning down 3D semiconductors. This enables better electrostatic control while avoiding degradation of transport properties. Among the 2D material crystals, MX 2 are specially interesting due to their semi-conductive properties.4-6 They have also been predicted to have robust performance for channel lengths down to 15 nm.7 Molybdenum disulfide (MoS 2 ), is commonly used as a representative of the MX 2 family. It has been demonstrated to be an interesting candidate for different applications such as low power logic devices, spintronic, valleytronic and also photo-voltaic devices. [8][9][10][11][12] It ...

show abstract

“…For example, Yokoyama et al [10] demonstrated mobility reduction from $1000 cm 2 /V s down to $10 cm 2 /V s when T B is scaled down from 9 nm to 3.5 nm in InGaAs-OI MOSFETs. Recently, Alian et al [11] reported higher electron mobility data ranging from 3000 cm 2 /V s for T B = 15 nm down to 110 cm 2 /V s for the 3 nmthick InGaAs device. Furthermore, previous theoretical studies have shown that (1 0 0)-oriented UTB InGaAs channels outperform SOI devices only above certain body thickness (around $5 nm) due to strong surface roughness and thickness-fluctuation-induced scattering caused by the low interface quality [12].…”

Section: Introductionmentioning

confidence: 96%

Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

Krivec

Poljak

Suligoj

2016

Solid-State Electronics

View full text Add to dashboard Cite

Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

Cited by 38 publications

References 4 publications

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Insight on the Characterization of MoS₂Based Devices and Requirements for Logic Device Integration

Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

Contact Info

Product

Resources

About

Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

Cited by 38 publications

References 4 publications

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Insight on the Characterization of MoS2Based Devices and Requirements for Logic Device Integration

Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

Contact Info

Product

Resources

About

Insight on the Characterization of MoS₂Based Devices and Requirements for Logic Device Integration