We present a review of our recent studies of BTI in FET devices fabricated in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies when a Si cap is used to passivate the channel and to fabricate a standard SiO2/HfO2 gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack. We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain engineering) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then invoke the model to understand the excessive BTI in other high-mobility channel gate stacks, as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.
The onset of the 22 nm node introduced 3-D Tri-Gate transistors into high-volume manufacturing for improved electrostatics. The next generations of Fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched Fin. In this work we have created InGaAs Fins down to 35 nm CD with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and Fin profile on electrical performance.
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