The influence of post-etch InGaAs fin profile on electrical performance

Abstract

The onset of the 22 nm node introduced 3-D Tri-Gate transistors into high-volume manufacturing for improved electrostatics. The next generations of Fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched Fin. In this work we have created InGaAs Fins down to 35 nm CD with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and Fin profile on electrical performance.

Overview of atomic layer etching in the semiconductor industry

“…This is in contrast to continuous etching of compound materials, which has high tendency to alter stoichiometry as one element is favorably removed relative to another. 4,[51][52][53] For ALE of SiO 2 , a fluorocarbon deposition approach was developed that provides both fluorine and carbon reactants in the modification step, as represented in Fig. 9(b).…”

“…111 These materials tend to have more complicated surfaces than silicon that require surface stoichiometry nearly identical to that of bulk to keep electronic properties from degrading. 4,111 The benefit of ALE in maintaining stoichiometry and providing smooth surfaces during directional etching is especially attractive for these materials. ALE has been studied on several III-V materials, include GaAs, 32,38,40,43,47,56,[64][65][66][67]98,[112][113][114][115][116] InGaAs, InP, AlGaAs, InAlAs, and AlGaN.…”

“…Surfaces have become a significant fraction of the device size and can appreciably affect device electronic properties. 3,4 There is significant impact to device performance from variability (including surface contributions), which increases current leakage and battery power loss and ultimately reduces yield due to failed devices. 2 With etching processes increasingly critical to state-of-the-art semiconductor devices, the tight control of etch variability offered by atomic layer etching (ALE) is necessary.…”

Low damage patterning of In0.53Ga0.47As film for its integration as n-channel in a fin metal oxide semiconductor field effect transistor architecture

“…4,5 One of the challenges of InGaAs integration as a channel in a FinFET architecture is the fabrication of the III-V fin. 6,7 It requires the development of the plasma etching process allowing nanometer scale fin definition, with vertical sidewalls and undamaged surfaces (top and sidewalls). Indeed, vertical-sidewall FinFETs have demonstrated better performance at low and moderately doped fins while extremely doped FinFETs are more performant when the fin sidewalls are tapered.…”

“…Indeed, vertical-sidewall FinFETs have demonstrated better performance at low and moderately doped fins while extremely doped FinFETs are more performant when the fin sidewalls are tapered. 6 Furthermore, plasma induced damage such as sidewall roughness 8 or modification of the surface stoichiometry 6 greatly degrades the MOS interface causing an important decline in the device reliability and electrical performance. These different aspects should be taken into account when carrying out advanced FinFETs.…”