Suitability of high-k gate oxides for III&#x2013;V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Abstract

We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.

Positive-bias temperature instability (PBTI) of GaN MOSFETs

“…The observations that we have made here are largely consistent with similar experiments on Si, SiC and III-V MOSFETs [15][16][17][18]. ∆VT appears to take place due to two mechanisms.…”

“…11 that graphs the correlation between the final values of ∆VT and ∆S after thermal detrapping following electrical stress at VGS,stress = 15 V. We see a strong linear correlation between the two. The proportionality constant seems to depend on T. Subthreshold swing degradation under PBTI has also been reported in Al2O3/InGaAs and HfO2/GaAs MOSFETs [18,20]. In our composite oxide samples, the permanent degradation of S is minor and a clear correlation with ∆VT does not emerge.…”

“…This phenomenon has been intensively studied in Si, SiC and various III-V MOS systems where it is sometimes referred to as bias-temperature instability (BTI) [12][13][14][15][16][17][18]. In Si n-channel MOSFETs with high-k gate dielectric, Positive Bias Temperature Instability (PBTI) is known to be caused by electron trapping in pre-existing oxide traps that causes a positive VT shift [12,13].…”

“…InGaAs n-MOSFETs with a high-k dielectric also have shown positive VT shifts after positive gate stress. This is believed to be due to pre-existing oxide traps and electron trap generation near the oxide/InGaAs interface [16][17][18].…”

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

“…The steeper voltage acceleration is indicative of a narrower border trap distribution (assuming a normal distribution), which can be seen as a projection of improved reliability at lower operating voltages. 31 The level of charge trapping in the samples can be quantified as…”