InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Abstract

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/lm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors

“…Device A and B are compared to TFETs from other publications in Figure 4 (b). Even if Device A is limited by the strong source depletion it still reaches approximately 40% lower S MIN compared to other III-V based TFETs [10,21,[25][26][27][28][29] at drain current levels that are approximately two orders of magnitude larger than Si-based TFETs [7]. Output data from Device A, B, and C is shown in Figure 5.…”

“…So far, the impact of source doping on the performance of these TFETs has not been studied. Previous studies, based on TFETs with other material systems [21,25,38], have demonstrated the importance of this parameter. Based on experimental data from devices with the nominally same heterojunction but with different doping levels, we here study the impact of source doping on the overall performance of vertical InAs/InGaAsSb/GaSb nanowire TFETs.…”

“…Since the first considerations to use TFET as steep slope device [3,4] the development of these devices has advanced rapidly. A large number of different material systems (carbon nanotubes [3], silicon [5][6][7], silicon-germanium [4,8,9], silicon-III-V [10][11][12], III-V [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], 2D-materials [31,32]) and geometries (lateral [3,[5][6][7][8][9][12][13][14]21,25,31,32], vertical [10,11,[15][16][17]…”

“…Further cycles are performed to reduce diameter of the channel region, which helps to improve the electrostatics of the devices[20,30]. The diameter of the InGaAsSb segments was also reduced to25 nm, while there was no noticeable etching of the GaSb. Directly after etching, a high-κ bilayer (1-nm Al 2 O 3 /4-nm HfO 2 ) was applied using atomic layer deposition at temperatures of 300 °C and 120 °C, respectively.…”

Decreasing Defect‐State Density of Al2O3/GaxIn1−xAs Device Interfaces with InOx Structures

“…An oxide/Ga x In 1− x As interface is frequently found as part of various device components (e.g., metal–oxide–semiconductor (MOS) high electron mobility transistor, structure, and IR detectors) currently used in electronics and in the design of many a potential future device (e.g., III–V MOS field‐effect transistor, and tunnel field‐effect transistor) . However, oxide/Ga x In 1− x As interfaces are usually considered as nonoptimized, adversely affecting the device performance: namely, they contain a high density of material defects that cause electronic defect states in the band‐gap area (gap states), which further increase the leakage current, nonradiative recombination, and Fermi‐level pinning, for example.…”