Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gateall-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ∼80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

No abstract

1  Abstract-We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb Tunneling Field-Effect Transistors integrated on Si substrates. The best subthreshold swing, 68 mV/dec at VDS = 0.3 V, was achieved for a device with 20 nm InAs diameter. The on-current for the same device was 35 µA/µm at VGS = 0.5 V and VDS = 0.5 V. The fabrication technique used allow downscaling of the InAs diameter down to 11 nm with a flexible gate placement.

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Tunnel Field-Effect Transistors with ability to operate well below the thermal limit (with a demonstrated 43 mV/decade at V DS = 0.1 V) are characterized in this work. Based on 88 devices, the impact of the low subthreshold swing on the overall performance is studied. Furthermore, correlation between parameters that are important for device characterization are determined.

In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on-and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from lateral InAs/GaSb are shown, as well as first results on integration of vertical InAs/GaSb nanowire TFETs on Si substrates.INDEX TERMS Tunnel field effect transistors (TFET), InAs, GaSb, III-V, broken gap.

No abstract