Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Abstract

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Record‐Low Subthreshold‐Swing Negative‐Capacitance 2D Field‐Effect Transistors

“…The SS min of reverse and forward sweep are 12.34 and 44.86 mV dec −1 , respectively, which are much lower than that of the NC‐FETs fabricated by MoS 2 /HZO (52.3 and 57.6 mV dec −1 , respectively), NW/HfO 2 system (15 and 54 mV dec −1 , respectively), and MoS 2 /CIPS system (28 and 39 mV dec −1 , respectively). [ 14,17,18 ] And, both of the average SS of dual sweeps are less than 60 mV dec −1 . These results suggest that the NC structure maintains well capacitance matching status in the subthreshold‐switching region.…”

“…Hence, it is urgent to develop novel prototype devices that can break the thermionic limit of SS to achieve sub-60 mV dec −1 . [3,4] To this end, several steep-slope device systems such as nanoelectromechanical FETs (NEMFETs), [5,6] tunnel FETs (T-FETs), [7,8] Dirac-source FETs (DS-FETs), [9] impact ionization FETs (II-FETs), [10] and negativecapacitance FETs (NC-FETs) [11][12][13][14][15][16][17][18] have been proposed and developed to realize sub-60 mV dec −1 SS potentially. For instance, compared with MOSFET, normal dielectric materials are replaced by ferroelectric/dielectric systems in NC-FETs to achieve low SS below 60 mV dec −1 under the condition of capacitance matching.…”

Ultra‐Steep‐Slope High‐Gain MoS2 Transistors with Atomic Threshold‐Switching Gate

“…[ 3 ] Therefore, reducing SS has become one of the critical challenges for large‐scale high‐performance integrated circuit development. [ 4 ] Several steep‐slope devices based on innovative structure or transport mechanisms, such as tunnel FETs (TFETs) [ 5 , 6 ] and negative capacitance FETs (NCFETs), [ 7 ] have been proposed to combat the “Boltzmann tyranny,” which have SS below 60 mV dec −1 at room temperature. However, in TFETs, because carriers are injected into the channel through band‐to‐band tunneling, drive current is greatly reduced.…”

Design of HeterojunctionTunnel Field-Effect Transistors with SiO2 isolation between Source and Drain for Low Power Application

“…Some of the facets that are particularly relevant to explain the acceleration of IoT technologies, i.e., the dimension of the devices, ability of the device to be integrated in the real world, the ability of the device for computational and memory capacities, etc. On that account, the development of device technologies is necessary to get the final objective of real and big-scale IoT applications [1][2]. The low power specially low stand-by power is the most essential requirement for devices in IoT application [3].…”