High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Abstract

We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gateall-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ∼80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

“…4. A comparison of the data in this letter with the trap response of gate-first fabricated InAs nanowire MOSFETs [19] indicates that the gate-last process has very similar trap densities as compared to the gate-first fabricated device. Furthermore, low-frequency (10 Hz -1 kHz) noise measurements (not shown) indicates comparable border trap densites deeper in the oxide for the two processing schemes.…”

“…4. a) Re (y 21 ) frequency dispersion of two devices: One fabricated using the gate-last process and one fabricated using the gate-first process from [19]. b) The calculated border trap density as a function of position in the oxide.…”

III–V compound semiconductor transistors—from planar to nanowire structures

“…Moreover, a modulation-doped GAA InGaAs NW-FET integrated on a Si substrate with excellent device properties 103 as well as vertical GAA InAs NW-FETs into which a thin InAs buffer layer had been introduced to reduce the access resistance toward the substrate 107 were recently demonstrated. Competitive radio frequency (RF) performance has been achieved, 108 and the fi rst RF circuits in the form of single-balanced down-conversion mixers operating up to 5 GHz were constructed.…”

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

“…18 Theses solutions result in a far different nanowire surface condition for the gate stack from those used for nanowire transistors. 5,6 In this work, we adopted a finger gate technique 35 with a minimized gate-source overlapping area to aggressively suppress the parasitic capacitance. On the basis of the technique, we provide detailed D it characterization and analysis on vertical wrap-gated InAs nanowires grown by metal−organic vapor phase epitaxy (MOVPE).…”

“…The first scheme, denoted as LT scheme below, followed previous reports of our group, 6 in which nanowires were grown at 420°C with a V/III ratio of 69. The molar fraction of AsH 3 and TMIn was 1.92 × 10 −4 and 2.79 × 10 −6 , respectively.…”