Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Charge‐carrier transport through an individually contacted bipyridyl‐dinitro oligophenylene‐ethynylene dithiol molecule (BPDN‐DT, see picture) and through a BP‐DT molecule was studied using the mechanically controllable break‐junction technique. BPDN‐DT exhibits a voltage‐induced switching between two distinct conductive states, in contrast to BP‐DT.

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

A generic process for fabricating vertical surround‐gate field‐effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n‐type Si nanowires grown on a p‐type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround‐gate FETs can be fabricated.

We present a statistical approach that combines comprehensive current-voltage data acquisition during the controlled manipulation of a molecular junction with subsequent statistical analysis. Thereby the most probable transport characteristics can be determined. The excellent sensitivity of this impartial approach to even subnanometer-long molecules is illustrated by benzene-1,4-dithiol and 4,4"-bis(acetylthiol)-2,2',5',2"-tetramethyl-[1,1';4',1"] terphenyl results.