We synthesized by atomic layer deposition (ALD) TiO2–IrO x alloys that enable high photovoltages and catalyze water oxidation on silicon metal–insulator–semiconductor (MIS) photoanodes. The ratio of TiO2 to IrO x was precisely controlled by varying the number of ALD cycles for each precursor. Silicon with a 2 nm surface SiO2 layer was coated with TiO2–IrO x alloys ranging in composition from 18 to 35% iridium relative to the sum of titanium and iridium concentrations. IrO x catalyzed oxygen evolution and imparted a high work function to the TiO2–IrO x alloys, enabling photovoltages during water oxidation that exceeded 600 mV. TiO2 imparted stability and inhibited corrosion of the underlying silicon light absorber. After annealing in forming gas (5% H2/95% N2), TiO2–IrO x alloys were stable for 12 h of continuous water oxidation in 1 M H2SO4. Key properties of the MIS junction affecting electrochemical operation were also extracted by electrochemical impedance spectroscopy. This work demonstrates that alloying by ALD is a promising approach for designing corrosion resistant Schottky contacts with optimized electronic and materials properties for catalyzed, solar driven water oxidation.

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

The effect of doping and diameter on the electrical properties of vapor-liquid-solid grown GaSb nanowires was characterized using long channel back-gated lateral transistors and top-gated devices. The measurements showed that increasing the doping concentration significantly increases the conductivity while reducing the control over the channel potential and shifting the threshold voltage, as expected. The highest average mobility was 85 cm2/V·s measured for an unintentionally doped GaSb nanowire with a diameter of 45 nm, whereas medium doped nanowires with large diameters (81 nm) showed a value of 153 cm2/V·s. The mobility is found to be independent of nanowire diameter in the range of 36 nm–68 nm, while the resistivity is strongly reduced with increasing diameter attributed to the surface depletion of charge carriers. The data are in good agreement with an analytical calculation of the depletion depth. A high transconductance was achieved by scaling down the channel length to 200 nm, reaching a maximum value of 80 μS/μm for a top-gated GaSb nanowires transistor with an ON-resistance of 26 kΩ corresponding to 3.9 Ω.mm. The lowest contact resistance obtained was 0.35 Ω·mm for transistors with the highest doping concentration.

Defects at the interface between InAs and a native or high permittivity oxide layer are one of the main challenges for realizing III-V semiconductor based metal oxide semiconductor structures with superior device performance. Here we passivate the InAs(100) substrate by removing the native oxide via annealing in ultra-high vacuum (UHV) under a flux of atomic hydrogen and growing a stoichiometry controlled oxide (thermal oxide) in UHV, prior to atomic layer deposition (ALD) of an Al2O3 high-k layer. The semiconductor-oxide interfacial stoichiometry and surface morphology are investigated by synchrotron based X-ray photoemission spectroscopy, scanning tunneling microscopy, and low energy electron diffraction. After thermal oxide growth, we find a thin non-crystalline layer with a flat surface structure. Importantly, the InAs-oxide interface shows a significantly decreased amount of In3+, As5+, and As0 components, which can be correlated to electrically detrimental defects. Capacitance-voltage measurements confirm a decrease of the interface trap density in gate stacks including the thermal oxide as compared to reference samples. This makes the concept of a thermal oxide layer prior to ALD promising for improving device performance if this thermal oxide layer can be stabilized upon exposure to ambient air.

The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance–voltage (C–V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm−2 eV−1 and 4 × 1012 cm−2 eV−1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C–V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.

A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

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elevated temperatures and UV light. To improve the stability of perovskite solar cells and LEDs, researchers have pursued numerous approaches including depositing hydrophobic coatings on top of perovskites absorbers, [23][24][25][26] device encapsulation [21,[27][28][29] and tuning the composition of perovskites. [30][31][32][33][34] Atomic layer deposited (ALD) metal oxides such as ZnO, Al 2 O 3 , and TiO 2 have been shown to be quite effective as a protection layer for perovskite optoelectronic devices. [35,36] Kim et al. [37] showed that ALD-TiO 2 could make the perovskite solar cells more resistant to elevated temperature and water vapor exposure. In reference, [36] low temperature ALD was utilized to deposit TiO 2 as an electron transport layer and Al 2 O 3 as a solar cell encapsulation layer. A final device including these protection layers was found to retain 97% of its original PCE after a thousand hours exposure to the ambient air. These results suggest that ALD-derived coatings provide a path to the device endurance required for commercial application of perovskite optoelectronic devices including perovskite solar cells, LEDs, and transistors.