Photoluminescence (PL) of organo-metal halide perovskite semiconductors can be enhanced by several orders of magnitude by exposure to visible light. We applied PL microscopy and super-resolution optical imaging to investigate this phenomenon with spatial resolution better than 10 nm using films of CH3NH3PbI3 prepared by the equimolar solution-deposition method, resulting in crystals of different sizes. We found that PL of ∼100 nm crystals enhances much faster than that of larger, micrometer-sized ones. This crystal-size dependence of the photochemical light passivation of charge traps responsible for PL quenching allowed us to conclude that traps are present in the entire crystal volume rather than at the surface only. Because of this effect, "dark" micrometer-sized perovskite crystals can be converted into highly luminescent smaller ones just by mechanical grinding. Super-resolution optical imaging shows spatial inhomogeneity of the PL intensity within perovskite crystals and the existence of <100 nm-sized localized emitting sites. The possible origin of these sites is discussed.

We investigate the surface quality of encapsulated Si:P δ-layers for the fabrication of multilayer devices with the potential to create architectures with sub 20 nm resolution in all three spatial dimensions. We use scanning tunneling microscopy to investigate how the dopant incorporation chemistry of the first active layer strongly affects the quality of the Si encapsulation which serves as the regrowth interface for the second active layer. Low temperature Hall measurements of the encapsulated layers indicate full dopant activation for incorporation temperatures between 250–750 °C with 20% higher carrier densities than previously observed.

We develop a super-saturation technique to extend the previously established doping density limit for ultra-high vacuum monolayer doping of silicon with phosphorus. Through an optimized sequence of PH3 dosing and annealing of the silicon surface, we demonstrate a 2D free carrier density of ns = (3.6 ± 0.1) × 1014 cm−2, ∼50% higher than previously reported values. We perform extensive characterization of the dopant layer resistivity, including room temperature depth-dependent in situ four point probe measurements. The dopant layers remain conductive at less than 1 nm from the sample surface and importantly, surpass the semiconductor industry target for ultra-shallow junction scaling of &lt;900 Ω◻−1 at a depth of 7 nm.

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor–oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor–oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

III−V semiconductors, such as InAs, with an ultrathin high-κ oxide layer have attracted a lot of interests in recent years as potential next-generation metal−oxide− semiconductor field-effect transistors, with increased speed and reduced power consumption. The deposition of the high-κ oxides is nowadays based on atomic layer deposition (ALD), which guarantees atomic precision and control over the dimensions. However, the chemistry and the reaction mechanism involved are still partially unknown. This study reports a detailed time-resolved analysis of the ALD of high-κ hafnium oxide (HfO x ) on InAs(100). We use ambient pressure X-ray photoemission spectroscopy and monitor the surface chemistry during the first ALD half-cycle, i.e., during the deposition of the metalorganic precursor. The removal of In and As native oxides, the adsorption of the Hf-containing precursor molecule, and the formation of HfO x are investigated simultaneously and quantitatively. In particular, we find that the generally used ligand exchange model has to be extended to a two-step model to properly describe the first half-cycle in ALD, which is crucial for the whole process. The observed reactions lead to a complete removal of the native oxide and the formation of a full monolayer of HfO x already during the first ALD half-cycle, with an interface consisting of In−O bonds. We demonstrate that a sufficiently long duration of the first half-cycle is essential for obtaining a high-quality InAs/HfO 2 interface.

Abrupt dopant profiles and low resistivity are highly sought after qualities in the silicon microelectronics industry and, more recently, in the development of an all epitaxial Si:P based quantum computer. If we increase the active carrier density in silicon to the point where the material becomes superconducting, while maintaining a low thermal budget, it will be possible to fabricate nanoscale superconducting devices using the highly successful technique of depassivation lithography. In this work, we investigate the dopant profile and activation in multiple high density Si:P δ-layers fabricated by stacking individual layers with intervening silicon growth. We determine that dopant activation is ultimately limited by the formation of P-P dimers due to the segregation of dopants between multilayers. By increasing the encapsulation thickness between subsequent layers, thereby minimizing the formation of these deactivating defects, we are able to achieve an active carrier density of ns = 4.5 ×10(14) cm(-2) for a triple layer. The results of electrical characterization are combined with those of secondary ion mass spectroscopy to construct a model that accurately describes the impact of P segregation on the final active carrier density in Si:P multilayers. Our model predicts that a 3D active carrier density of 8.5 × 10(20) cm(-3) (1.7 atom %) can be achieved.

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon-phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.

Defects at the interface between InAs and a native or high permittivity oxide layer are one of the main challenges for realizing III-V semiconductor based metal oxide semiconductor structures with superior device performance. Here we passivate the InAs(100) substrate by removing the native oxide via annealing in ultra-high vacuum (UHV) under a flux of atomic hydrogen and growing a stoichiometry controlled oxide (thermal oxide) in UHV, prior to atomic layer deposition (ALD) of an Al2O3 high-k layer. The semiconductor-oxide interfacial stoichiometry and surface morphology are investigated by synchrotron based X-ray photoemission spectroscopy, scanning tunneling microscopy, and low energy electron diffraction. After thermal oxide growth, we find a thin non-crystalline layer with a flat surface structure. Importantly, the InAs-oxide interface shows a significantly decreased amount of In3+, As5+, and As0 components, which can be correlated to electrically detrimental defects. Capacitance-voltage measurements confirm a decrease of the interface trap density in gate stacks including the thermal oxide as compared to reference samples. This makes the concept of a thermal oxide layer prior to ALD promising for improving device performance if this thermal oxide layer can be stabilized upon exposure to ambient air.