Investigating the regrowth surface of Si:P δ-layers toward vertically stacked three dimensional devices

Abstract

We investigate the surface quality of encapsulated Si:P δ-layers for the fabrication of multilayer devices with the potential to create architectures with sub 20 nm resolution in all three spatial dimensions. We use scanning tunneling microscopy to investigate how the dopant incorporation chemistry of the first active layer strongly affects the quality of the Si encapsulation which serves as the regrowth interface for the second active layer. Low temperature Hall measurements of the encapsulated layers indicate full dopant activation for incorporation temperatures between 250–750 °C with 20% higher carrier densities than previously observed.

Optimizing dopant activation in Si:P double δ-layers

“…Low-temperature magnetotransport measurements confirm that all dopants are electrically activated after encapsulation [13], giving a maximal n s ¼ 2:4 Â 10 14 cm À2 . However, the presence of the PH x fragments, H and ejected Si on the surface result in limited Si adatom diffusion, reducing the quality of the homoepitaxial Si encapsulation with a corresponding increase in surface roughness [13,15,16]. Fig.…”

“…As a result, only a quarter of a monolayer of dopants remains after a 550 3 C anneal, giving n s ¼ 1:9 Â 10 14 cm À2 . However, the surface is atomically flat, providing a more ideal starting surface for the overgrowth of high quality, epitaxial silicon [13].…”

“…The Si:P material system is of particular interest because it has been recently integrated with STM lithography for the fabrication of atomic-scale devices [12]. In this work, we investigate how the preparation of this first Si:P dÀlayer, [13] influences the dopant activation and transport properties of the second P layer. A detailed understanding of the effects of Si crystal growth on the activation in each of the layers is achieved through a combination of STM and low-temperature magnetotransport measurements.…”

Heterogeneous nucleation of pits via step pinning during Si(100) homoepitaxy

“…Evolving Si quantum computing technologies are demanding epitaxial thin films with exceptionally flat and abrupt interfaces, ideally to the single-atomic-layer limit [1][2][3][4][5]. For a few leading qubit platforms, e.g.…”

Silicon epitaxy on H-terminated Si (100) surfaces at 250 °C

“…It has also been reported that epitaxial growth of silicon can occur at temperatures as low as room temperature [15] , and that Si film growth at room temperature up to several monolayers’ thickness has been successfully used as a locking layer to maintain ultra-sharp dopant profiles [16] . Electrical measurements by McKibbin et al [17] show 100% dopant activation at 250 °C encapsulation temperatures. Furthermore, it was shown that epitaxial encapsulation above 270 °C leads to dopant segregation with no improvement in the quality of overgrowth with a notable 50 % drop in carrier concentration.…”