Molecular beam epitaxy and scanning tunneling microscopy (STM) patterning are combined to form highly doped, planar devices in silicon at the atomic level. The absolute device location is registered to microscopic markers (see image; scale bar: 50 μm) for the alignment of surface contacts, enabling the correlation of the electrical properties of atomically controlled devices such as nanowires, tunnel junctions, and nanodots to the dopant location, monitored using high‐resolution STM techniques.

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon-phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.

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We present a combined scanning tunneling microscopy (STM) and low-temperature magnetotransport study of Si:P δ-doped layers on vicinal Si(001) substrates. The substrates were misoriented 4° toward [110] resulting in a high step density on the starting growth surface. Atomically resolved STM was used to study all stages of the fabrication. We find only a weak influence of the high step density and discuss the implications for the fabrication δ-doped layers and planar nanoscale Si:P devices by scanning tunneling lithography.

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We investigate the conduction properties of an embedded, highly phosphorus-doped nanowire with a width of 8nm lithographically defined by scanning tunneling microscope based patterning of a hydrogen-terminated Si(100):H surface. Four terminal I-V measurements show that ohmic conduction is maintained within the investigated temperature range from 35K down to 1.3K. A prominent resistance increase is observed below ∼4K which is attributed to a crossover into the strong localization regime. The low temperature conductance follows a one-dimensional variable range hopping model accompanied by positive magnetoresistance which dominates over weak localization effects at low temperature.