We determine the detailed differences in geometry and band structure between wurtzite (Wz) and zinc blende (Zb) InAs nanowire (NW) surfaces using scanning tunneling microscopy/spectroscopy and photoemission electron microscopy. By establishing unreconstructed and defect-free surface facets for both Wz and Zb, we can reliably measure differences between valence and conduction band edges, the local vacuum levels, and geometric relaxations to the few-millielectronvolt and few-picometer levels, respectively. Surface and bulk density functional theory calculations agree well with the experimental findings and are used to interpret the results, allowing us to obtain information on both surface and bulk electronic structure. We can thus exclude several previously proposed explanations for the observed differences in conductivity of Wz-Zb NW devices. Instead, fundamental structural differences at the atomic scale and nanoscale that we observed between NW surface facets can explain the device behavior.

Using scanning tunneling microscopy and spectroscopy we study the atomic scale geometry and electronic structure of GaAs nanowires exhibiting controlled axial stacking of wurtzite (Wz) and zinc blende (Zb) crystal segments. We find that the nonpolar low-index surfaces {110}, {101[overline]0}, and {112[overline]0} are unreconstructed, unpinned, and without states in the band gap region. Direct comparison between Wz and Zb GaAs reveal a type-II band alignment and a Wz GaAs band gap of 1.52 eV.

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor–oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor–oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

We present a study of InAs/InSb heterostructured nanowires by X-ray photoemission spectroscopy (XPS), scanning tunneling microscopy (STM), and in-vacuum electrical measurements. Starting with pristine nanowires covered only by the native oxide formed through exposure to ambient air, we investigate the effect of atomic hydrogen cleaning on the surface chemistry and electrical performance. We find that clean and unreconstructed nanowire surfaces can be obtained simultaneously for both InSb and InAs by heating to 380 ± 20 °C under an H2 pressure 2 × 10(-6) mbar. Through electrical measurement of individual nanowires, we observe an increase in conductivity of 2 orders of magnitude by atomic hydrogen cleaning, which we relate through theoretical simulation to the contact-nanowire junction and nanowire surface Fermi level pinning. Our study demonstrates the significant potential of atomic hydrogen cleaning regarding device fabrication when high quality contacts or complete control of the surface structure is required. As hydrogen cleaning has recently been shown to work for many different types of III-V nanowires, our findings should be applicable far beyond the present materials system.

While shell growth engineering to the atomic scale is important for tailoring semiconductor nanowires with superior properties, a precise knowledge of the surface structure and morphology at different stages of this type of overgrowth has been lacking. We present a systematic scanning tunneling microscopy (STM) study of homoepitaxial shell growth of twinned superlattices in zinc blende InAs nanowires that transforms {111}A/B-type facets to the nonpolar {110}-type. STM imaging along the nanowires provides information on different stages of the shell growth revealing distinct differences in growth dynamics of the crystal facets and surface structures not found in the bulk. While growth of a new surface layer is initiated simultaneously (at the twin plane interface) on the {111}A and {111}B nanofacets, the step flow growth proceeds much faster on {111}A compared to {111}B leading to significant differences in roughness. Further, we observe that the atomic scale structures on the {111}B facet is different from its bulk counterpart and that shell growth on this facet occurs via steps perpendicular to the ⟨112⟩B-type directions.

The perfect switching between crystal phases with different electronic structure in III-V nanowires allows for the design of superstructures with quantum wells only a single atomic layer wide. However, it has only been indirectly inferred how the electronic structure will vary down to the smallest possible crystal segments. We use low-temperature scanning tunneling microscopy and spectroscopy to directly probe the electronic structure of Zinc blende (Zb) segments in Wurtzite (Wz) InAs nanowires with atomic-scale precision. We find that the major features in the band structure change abruptly down to a single atomic layer level. Distinct Zb electronic structure signatures are observed on both the conduction and valence band sides for the smallest possible Zb segment: a single InAs bilayer. We find evidence of confined states in the region of both single and double bilayer Zb segments indicative of the formation of crystal segment quantum wells due to the smaller band gap of Zb as compared to Wz. In contrast to the internal electronic structure of the nanowire, surface states located in the band gap were found to be only weakly influenced by the presence of the smallest Zb segments. Our findings directly demonstrate the feasibility of crystal phase switching for the ultimate limit of atomistic band structure engineering of quantum confined structures. Further, it indicates that band gap values obtained for the bulk are reasonable to use even for the smallest crystal segments. However, we also find that the suppression of surface and interface states could be necessary in the use of this effect for engineering of future electronic devices.

Using scanning tunneling microscopy, we evaluate the surface structure and morphology down to the atomic scale for micrometers along Au-free grown InAs nanowires (NWs) free from native oxide. We find that removal of the native oxide (which covers the NWs upon exposure to the ambient air) using atomic hydrogen does not alter the underlying step structure. Imaging with sub-nanometer resolution along the NWs, we find an extremely low tapering (diameter change along the NW) of 1.7 ± 0.5 Åμm(-1). A surface morphology with monolayer high islands, whose shape was influenced by stacking faults, was found to cover the NWs and was attributed to the decomposed native oxide. The appearance of point defects in the form of As-vacancies at the surface is analyzed and we set limits to the amount of carbon impurities in the NWs.

Defects at the interface between InAs and a native or high permittivity oxide layer are one of the main challenges for realizing III-V semiconductor based metal oxide semiconductor structures with superior device performance. Here we passivate the InAs(100) substrate by removing the native oxide via annealing in ultra-high vacuum (UHV) under a flux of atomic hydrogen and growing a stoichiometry controlled oxide (thermal oxide) in UHV, prior to atomic layer deposition (ALD) of an Al2O3 high-k layer. The semiconductor-oxide interfacial stoichiometry and surface morphology are investigated by synchrotron based X-ray photoemission spectroscopy, scanning tunneling microscopy, and low energy electron diffraction. After thermal oxide growth, we find a thin non-crystalline layer with a flat surface structure. Importantly, the InAs-oxide interface shows a significantly decreased amount of In3+, As5+, and As0 components, which can be correlated to electrically detrimental defects. Capacitance-voltage measurements confirm a decrease of the interface trap density in gate stacks including the thermal oxide as compared to reference samples. This makes the concept of a thermal oxide layer prior to ALD promising for improving device performance if this thermal oxide layer can be stabilized upon exposure to ambient air.