Low Trap Density in InAs/High-<i>k</i> Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Wu, Jun; Babadi, Aein Shiri; Jacobsson, Daniel; Colvin, Jovana; Yngman, Sofie; Timm, Rainer; Lind, Erik; Wernersson, Lars‐Erik

doi:10.1021/acs.nanolett.5b05253

Cited by 32 publications

(25 citation statements)

References 41 publications

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“…The PL spectra shown in Figure a also support the proposed defect levels of the three samples. The results suggest that the polytypic structures are not beneficial for the transfer and separation of photogenerated electrons and holes, which is consistent with previous works that have reported that stacking faults decrease mobilities …”

Section: Resultssupporting

confidence: 92%

“…The piezoelectric properties of CdS NWs were deteriorated by the presence of alternating zinc blende (ZB)–wurtzite (WZ) phases . A number of previous works have reported that stacking faults also significantly influence the electrical properties of NWs . Therefore, the control of stacking faults has been recognized as a powerful strategy for tuning the mechanical and electrical properties of NWs.…”

Section: Introductionmentioning

confidence: 99%

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Bent Polytypic ZnSe and CdSe Nanowires Probed by Photoluminescence

Kim

Park

et al. 2017

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Nanowires (NWs) have witnessed tremendous development over the past two decades owing to their varying potential applications. Semiconductor NWs often contain stacking faults due to the presence of coexisting phases, which frequently hampers their use. Herein, it is investigated how stacking faults affect the optical properties of bent ZnSe and CdSe NWs, which are synthesized using the vapor transport method. Polytypic zinc blende-wurtzite structures are produced for both these NWs by altering the growth conditions. The NWs are bent by the mechanical buckling of poly(dimethylsilioxane), and micro-photoluminescence (PL) spectra were then collected for individual NWs with various bending strains (0-2%). The PL measurements show peak broadening and red shifts of the near-band-edge emission as the bending strain increases, indicating that the bandgap decreases with increasing the bending strain. Remarkably, the bandgap decrease is more significant for the polytypic NWs than for the single phase NWs. This work provides insights into flexible electronic devices of 1D nanostructures by engineering the polytypic structures.

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Section: Resultssupporting

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Bent Polytypic ZnSe and CdSe Nanowires Probed by Photoluminescence

Kim

Park

et al. 2017

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“…Donor-like traps were introduced at this interface. Their energetic distribution was extracted from CV measurements of InAs nanowires [13] and adapted here. Traps may also exist in the band gap at the InGaAsSb/oxide interface.…”

Section: Trap Distribution and Modeling Of Trap-assisted Tunnelingmentioning

confidence: 99%

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Sant¹,

Memišević²,

Wernersson³

et al. 2018

CompoNano

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Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxideinterface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation setup. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation setup is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found.

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“…Donor-like defects were assumed and placed at the InAs/oxide interface. Their energetic distribution was adapted from an earlier study [26]. Defects at the InGaAsSb/oxide interface are screened by the central region of the nanowire due to its high doping concentration.…”

mentioning

confidence: 99%

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Memišević

Hellenbrand²,

Lind

et al. 2017

Nano Lett.

Self Cite

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Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

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Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Cited by 32 publications

References 41 publications

Bent Polytypic ZnSe and CdSe Nanowires Probed by Photoluminescence

Bent Polytypic ZnSe and CdSe Nanowires Probed by Photoluminescence

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

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