Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.
III-V compound semiconductors are indispensable materials for today's high-end electronic and optoelectronic devices and are being explored for next-generation transistor logic and quantum technologies. III-V surfaces and interfaces play the leading role in determining device performance, and therefore, methods to control their electronic properties have been developed. Typically, surface passivation studies demonstrated how to limit the density of surface states. Strain has been widely used to improve the electronic transport properties and optoelectronic properties of III-Vs, but the potential of this technology to modify the surface properties still remains to be explored. Here we show that uniaxial stress induces a shift in the energy of the surface states of III-V nanowires, modifying their electronic properties. We demonstrate this phenomenon by modulating the conductivity of InAs nanowires over 4 orders of magnitude with axial strain ranging between -2.5% in compression and 2.1% in tension. The band bending at the surface of the nanostructure is modified from accumulation to depletion reversibly and reproducibly. We provide evidence of this physical effect using a combination of electrical transport measurement, Raman spectroscopy, band-structure modeling, and technology computer aided design (TCAD) simulations. With this methodology, the deformation potentials for the surface states are quantified. These results reveal that strain technology can be used to shift surface states away from energy ranges in which device performance is negatively affected and represent a novel route to engineer the electronic properties of III-V devices.
Articles you may be interested inCompressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors
In this paper a simulation study of the effect of conduction and valence band offsets on the subthreshold swing (SS) of a double-gate tunnel field-effect transistor (TFET) with gate-overlapped source is presented. The simulations show that if the pn-junction and the hetero-junction coincide, the band offsets can significantly improve the SS by suppressing the so-called point tunneling at the pn-junction. It turns out that the performance of an n-channel TFET is determined by the direct conduction band offset whereas that of a p-channel TFET is mainly effected by the energy difference between the light hole bands of the two materials. Thus, the performance of the hetero-junction TFET can be improved by selecting material systems with high conduction or valence band offsets. The misalignment between the pn-junction and the hetero-junction is shown to degrade the SS. The above-described band-offset engineering has been applied to the GeSn/SiGeSn hetero-structure system with and without strain. Simulations of GeSn/SiGeSn hetero-TFETs with band-to-band-tunneling parameters determined from pseudopotential calculations show that compressive strain in GeSn widens the design space for TFET application while tensile strain reduces it.INDEX TERMS Tunnel FETs, GeSn-SiGeSn hetero structures, band offset optimization.
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