Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Abstract

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Low-Frequency Noise in III–V Nanowire TFETs and MOSFETs

“…As was shown for example in [2] and [12], the LFN behavior in TFETs is dominated by the 10-20 nm of the gate/channel closest to the junction, which explains how only very few defects contribute to the LFN characteristics. In fact, in many of the TFETs studied here, for certain bias conditions we were able to measure Random Telegraph Signal (RTS) noise [7], which is caused by only one individual defect, and agrees well with the observation of γ approaching values of two. The small gate area affecting LFN in TFETs also explains why the levels of the gate area normalized equivalent input gate voltage noise PSD S V f b ×L G ×W G for MOSFETs and TFETs in Fig.…”

“…In the case of the TFETs here, it is known that the off-state was affected by thermionic emission through defect-assisted tunneling [6], [7]. Since the TFET off-current after the junction is governed by drift-diffusion, mobility fluctuations can occur in the TFET off-current as well.…”

“…After etching, identical high-κ gate oxides (1 nm/4 nm Al 2 O 3 /HfO 2 atomic layer deposition, effective oxide thickness ≈ 1.4 nm) and sputtered W metal gates were applied for all devices. Source, gate, and drain were separated by spacers, details on the processing schemes can be found in [5] for MOSFETs, and in [6] (GaSb) and [7] (InGaAsSb) for TFETs. Fig.…”

Recent Advances in Low‐Dimensional Heterojunction‐Based Tunnel Field Effect Transistors

“…He received his Ph.D. degree in physics from Wuhan University in 2009. [31] On the other hand, too small bandgap will degrade the off-state behavior, which also should be avoided. His research involves design and synthesis of lowdimensional materials and processing methods for highperformance electronics.…”

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors

“…Since the first considerations to use TFET as steep slope device [3,4] the development of these devices has advanced rapidly. A large number of different material systems (carbon nanotubes [3], silicon [5][6][7], silicon-germanium [4,8,9], silicon-III-V [10][11][12], III-V [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], 2D-materials [31,32]) and geometries (lateral [3,[5][6][7][8][9][12][13][14]21,25,31,32], vertical [10,11,[15][16][17]…”