Recent Advances in Low‐Dimensional Heterojunction‐Based Tunnel Field Effect Transistors

Abstract

Since the continuous scaling down of the transistor channel length, extraordinary improvement is achieved in the switching speed. However, the rising leakage current degrades the power consumption seriously. In this regard, reducing supply voltage might be the most effective method. This requirement can be fulfilled well by tunnel field‐effect transistors (TFETs), because carriers transport via a band‐to‐band tunneling manner in the TFETs. Relying on the special transport mechanism, the TFETs often require band structure modulations and steep interfaces without trap state, which are challenging for bulk materials. Therefore, these challenges have boosted TFET designs based on low‐dimensional materials ranging from Si/Ge nanowires to state‐of‐art van der Waals heterostructures. Here, the key concepts of the currently developed TFETs are studied from the aspects of structure, material, transportation characteristic, and mechanism. According to the heterojunction bonding types, they can be divided into lateral and vertical TFETs in general. Furthermore, other related transistors based on tunneling are also included. Emerging problems and promotion methods toward these TFETs are introduced with the assistance of simulations. The main goal is to introduce the frontiers of TFET explorations and provide readers with a perspective on how to realize TFET applications in the future.

Mobility Extraction in 2D Transition Metal Dichalcogenide Devices—Avoiding Contact Resistance Implicated Overestimation

“…applications including post-complementary metal-oxide semiconductor (CMOS) logic, [1][2][3] memory, [4][5][6] flexible electronics, [7,8] and hardware-relevant artificial intelligence development. [9][10][11] The carrier mobility (μ) is a central parameter in characterizing electron and hole transport in a material.…”

Quantum Transport in Monolayer α‐CS Field‐Effect Transistors

“…2D semiconductors have been extensively researched in the past decade, which is identified as the promising channels of sub‐5‐nm metal‐oxide‐semiconductor field‐effect transistors (FETs) for the next‐generation electronics, [ 1–6 ] due to their tremendous advantages of smooth surface, nanoscale thickness, good gate electrostatics, and suppressed carrier scattering. [ 7–10 ] Recently, many 2D semiconductors such as 2D MoS 2 , [ 11 ] black phosphorene (BP), [ 12 ] InSe, [ 13–16 ] Bi 2 O 2 Se [ 17 ] have been intensively explored theoretically and experimentally. [ 18–24 ] However, 2D MoS 2 suffers from a low mobility (200 cm 2 V −1 s −1 ), resulting in a low on‐state current ( I on ), which cannot be applied to the high‐performance (HP) electronics.…”

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

“…Moreover, the supply voltage (VDD) needs to be lowered with device downsizing for low power applications. After undergoing a thorough literature surveys of recent times [15][16][17][18][19][20], graphene nanoribbon has been introduced over Si channel. Graphene, being an excellent mechanical and electronic property holder; has been used as nanoribbon to tune the energy band gap and thereby enhancing the switching ratio (ION/IOFF).…”