Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Sant, Saurabh; Memišević, Elvedin; Wernersson, Lars‐Erik; Schenk, Andreas

doi:10.21494/iste.op.2018.0221

Cited by 4 publications

(4 citation statements)

References 21 publications

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“…It is worth mentioning that our results, in this case study, are in agreement with the results of [23] and [35] which reported that the impact of bulk traps on the performance of hetero-junction TFETs is minor while the impact of heterointerface traps and oxide-interface traps are dominant. So, it is important to investigate the impact of oxide-interface traps on the transfer characteristics of the proposed SS-TFET design.…”

Section: Impact Of Non-idealitiessupporting

confidence: 92%

“…Additionally, the impact of variation of the effective oxide thickness (EOT) is presented. Moreover, the influence of different types of non-idealities like hetero-interface traps, oxide interface traps and bulk traps, which may arise from fabrication processes [22,23], on the device performance is studied. Finally, the conclusions are drawn in the last section.…”

Section: Introductionmentioning

confidence: 99%

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A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Elnaggar

Shaker

Fedawy

2019

Semicond. Sci. Technol.

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In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TFET by using the combined two methods. The ON to OFF current ratio (I ON /I OFF ) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (g m ) and unit-gain cutoff frequency ( f T ) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (t phl ) and overshoot voltage (V p ) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TFET over Si-TFET that makes the proposed design more advantageous in the field of analog and digital applications.

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Section: Impact Of Non-idealitiessupporting

confidence: 92%

Section: Introductionmentioning

confidence: 99%

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Elnaggar

Shaker

Fedawy

2019

Semicond. Sci. Technol.

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“…As the gate underlap distance from source end increases, the influence of electrostatic gate control over the active region of the device decreases. 21 Hence, the magnitude of band lowering at the hetero interface decreases despite the shell radius as depicted in Fig. 4(ii).…”

Section: Resultsmentioning

confidence: 88%

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Joseph

Singh

Nagarajan

et al. 2021

ECS J. Solid State Sci. Technol.

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A comprehensive investigation with the help of 3D device simulation, we demonstrate the impact of fringing field on shell radius of InAs-GaSb core–shell nanowire n-channel tunnel field effect transistor (TFET) in this paper. Increase in shell radius intensifies the magnitude of fringing electric field towards shell region. This results in generation of depletion zone in the shell near the gate edge affects the device performance metrics such as on current and threshold voltage. It is demonstrated that by appropriate gate engineering the influence of fringing electric field can be circumvent. High-k spacer dielectric at the gate underlap shows improvement in device performance metrics such as on current with sub 2.3 k B T q subthreshold swing. An investigation of the effect of drain voltage on the device characteristics exhibits the privation of tunneling resistance limited region. Furthermore, the output characteristics for such an architecture bear a resemblance to long channel MOSFET (metal oxide semiconductor field effect transistor).

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“…Based on recent TCAD modeling works of trap-related effects in a start-of-the-art experimental III-V TFET [7,8], we here propose to extend an existing Verilog-A compact model for an ideal TFET [9,10] to the respective parasitic effects of junction bulk traps and oxide interface traps. Therefore, for the first time, we manage to elucidate the impact of traps in a realistic TFET on its circuit-level power-performance (PP) metrics through SPICE simulations on a ring oscillator (RO) circuit test bench.…”

Section: Introductionmentioning

confidence: 99%

Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET

Yang

Yakimets

Sant

et al. 2018

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ~5x iso-frequency energy penalty in the desired low-supply-voltage domain (≤ 0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.

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Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Cited by 4 publications

References 21 publications

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET

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