2016
DOI: 10.1063/1.4945430
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ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment

Abstract: The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance–voltage (C–V) measurements exhibit a total trap density profile with a minimum of 1 × … Show more

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Cited by 14 publications
(14 citation statements)
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“…Namely, in [25] it is observed that there is a maximum value of Δ fb between the two Al 2 O 3 /HfO 2 thicknesses ratios of 2.5 nm/3.0 nm and 0.5 nm/2.5 nm higher than or equal to 0.4 V. From our experiment a higher value of 1.2 V is obtained for the thicknesses ratio 1.0 nm/2.5 nm. This value is substantially higher than the value reported for pure HfO 2 [26] under similar conditions. Therefore, it can be concluded that the insertion of Al 2 O 3 between HfO 2 layers for the given thickness ratio substantially increases the trapping in the high-stacked layer.…”
Section: − Hysteresiscontrasting
confidence: 70%
“…Namely, in [25] it is observed that there is a maximum value of Δ fb between the two Al 2 O 3 /HfO 2 thicknesses ratios of 2.5 nm/3.0 nm and 0.5 nm/2.5 nm higher than or equal to 0.4 V. From our experiment a higher value of 1.2 V is obtained for the thicknesses ratio 1.0 nm/2.5 nm. This value is substantially higher than the value reported for pure HfO 2 [26] under similar conditions. Therefore, it can be concluded that the insertion of Al 2 O 3 between HfO 2 layers for the given thickness ratio substantially increases the trapping in the high-stacked layer.…”
Section: − Hysteresiscontrasting
confidence: 70%
“…Due to thermally excited minority carriers, there is an increase in capacitance again once the bias is reduced below −1 V, which is typical at room temperature for narrow band gap III–V materials such as InAs. 27 − 29 As the frequency is increased, the capacitive contributions from minority carriers and defect states are reduced. For both samples B ( Figure 5 a) and E ( Figure 5 c), the typical “butterfly”-shaped CV curves are measured, exhibiting two distinct peaks arising from the increased capacitance during polarization switching.…”
Section: Resultsmentioning
confidence: 99%
“…77 The charge trapping effects of gate-oxides on InAs nanowires typically onset at negative gate voltage and become more pronounced with increasingly negative voltage. [78][79][80] Indeed, in Supplementary Fig. S16 we show gate sweeps in both directions for the top-gate and back-gate on Device 2.…”
Section: Electrical Characterisation Of Hall-configuration Nanofin De...mentioning
confidence: 98%