We synthesized by atomic layer deposition (ALD) TiO2–IrO x alloys that enable high photovoltages and catalyze water oxidation on silicon metal–insulator–semiconductor (MIS) photoanodes. The ratio of TiO2 to IrO x was precisely controlled by varying the number of ALD cycles for each precursor. Silicon with a 2 nm surface SiO2 layer was coated with TiO2–IrO x alloys ranging in composition from 18 to 35% iridium relative to the sum of titanium and iridium concentrations. IrO x catalyzed oxygen evolution and imparted a high work function to the TiO2–IrO x alloys, enabling photovoltages during water oxidation that exceeded 600 mV. TiO2 imparted stability and inhibited corrosion of the underlying silicon light absorber. After annealing in forming gas (5% H2/95% N2), TiO2–IrO x alloys were stable for 12 h of continuous water oxidation in 1 M H2SO4. Key properties of the MIS junction affecting electrochemical operation were also extracted by electrochemical impedance spectroscopy. This work demonstrates that alloying by ALD is a promising approach for designing corrosion resistant Schottky contacts with optimized electronic and materials properties for catalyzed, solar driven water oxidation.

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

The effect of doping and diameter on the electrical properties of vapor-liquid-solid grown GaSb nanowires was characterized using long channel back-gated lateral transistors and top-gated devices. The measurements showed that increasing the doping concentration significantly increases the conductivity while reducing the control over the channel potential and shifting the threshold voltage, as expected. The highest average mobility was 85 cm2/V·s measured for an unintentionally doped GaSb nanowire with a diameter of 45 nm, whereas medium doped nanowires with large diameters (81 nm) showed a value of 153 cm2/V·s. The mobility is found to be independent of nanowire diameter in the range of 36 nm–68 nm, while the resistivity is strongly reduced with increasing diameter attributed to the surface depletion of charge carriers. The data are in good agreement with an analytical calculation of the depletion depth. A high transconductance was achieved by scaling down the channel length to 200 nm, reaching a maximum value of 80 μS/μm for a top-gated GaSb nanowires transistor with an ON-resistance of 26 kΩ corresponding to 3.9 Ω.mm. The lowest contact resistance obtained was 0.35 Ω·mm for transistors with the highest doping concentration.

Defects at the interface between InAs and a native or high permittivity oxide layer are one of the main challenges for realizing III-V semiconductor based metal oxide semiconductor structures with superior device performance. Here we passivate the InAs(100) substrate by removing the native oxide via annealing in ultra-high vacuum (UHV) under a flux of atomic hydrogen and growing a stoichiometry controlled oxide (thermal oxide) in UHV, prior to atomic layer deposition (ALD) of an Al2O3 high-k layer. The semiconductor-oxide interfacial stoichiometry and surface morphology are investigated by synchrotron based X-ray photoemission spectroscopy, scanning tunneling microscopy, and low energy electron diffraction. After thermal oxide growth, we find a thin non-crystalline layer with a flat surface structure. Importantly, the InAs-oxide interface shows a significantly decreased amount of In3+, As5+, and As0 components, which can be correlated to electrically detrimental defects. Capacitance-voltage measurements confirm a decrease of the interface trap density in gate stacks including the thermal oxide as compared to reference samples. This makes the concept of a thermal oxide layer prior to ALD promising for improving device performance if this thermal oxide layer can be stabilized upon exposure to ambient air.