Impact of doping and diameter on the electrical properties of GaSb nanowires

Abstract

The effect of doping and diameter on the electrical properties of vapor-liquid-solid grown GaSb nanowires was characterized using long channel back-gated lateral transistors and top-gated devices. The measurements showed that increasing the doping concentration significantly increases the conductivity while reducing the control over the channel potential and shifting the threshold voltage, as expected. The highest average mobility was 85 cm2/V·s measured for an unintentionally doped GaSb nanowire with a diameter of 45 nm, whereas medium doped nanowires with large diameters (81 nm) showed a value of 153 cm2/V·s. The mobility is found to be independent of nanowire diameter in the range of 36 nm–68 nm, while the resistivity is strongly reduced with increasing diameter attributed to the surface depletion of charge carriers. The data are in good agreement with an analytical calculation of the depletion depth. A high transconductance was achieved by scaling down the channel length to 200 nm, reaching a maximum value of 80 μS/μm for a top-gated GaSb nanowires transistor with an ON-resistance of 26 kΩ corresponding to 3.9 Ω.mm. The lowest contact resistance obtained was 0.35 Ω·mm for transistors with the highest doping concentration.

p-GaAs Nanowire Metal–Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

“…Our sub-threshold swing of 62 mV/dec significantly surpasses that obtained by Dey et al and Babadi et al above. Our peak transconductance g m = 1.3 µS/µm (normalised to channel circumference) is comparable with that obtained by Dey et al 19 Our normalised on-resistance is 137 Ω.mm, which is 65% lower than the device reported by Dey et al but ∼ 35 times higher than Babadi et al 20 Improvement in our normalised on-resistance should be possible by reducing the channel length and/or increasing the shell doping density to improve the contact resistance and then compensating with increased gate-etch depth to maintain gate-performance. The hole mobility is challenging to calculate for our device due to the absence of an oxide, but we can provide a reasonable estimate.…”

“…6,8 A key aspect in vertical array devices is that the gate-length is no longer constrained by lithography and instead controlled by layer thicknesses during processing, facilitating scaling to sub-100 nm gate length. This pathway has already been taken for p-GaSb, with the single horizontal nanowire devices of Dey et al 19 and Babadi et al 20 translated into vertical nanowire array structures by, e.g., Svensson et al 21 and…”

“…This improved the peak transconductance to g m = 80 µS/µm but also led to a significantly reduced subthreshold swing of 820 mV/dec. 20 A measurement of hole mobility was not provided in Dey et al 19 but Babadi et al 20 obtained a peak hole mobility of 153 cm 2 /Vs. Our sub-threshold swing of 62 mV/dec significantly surpasses that obtained by Dey et al and Babadi et al above.…”

A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

“…1. In the case of GaSb growth, significant background doping is present attributed to point defects (~10 16 ) [15]. By utilizing the Gibbs-Thomson effect during VLS growth, the GaSb growth rate can be significantly reduced for smaller gold particle sizes [16] A Self-aligned Gate-last Process applied to All- (diameter < 30 nm) which enables length control of the two separate materials in the heterojunction nanowires [17].…”

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors

“…The exact evaluation of the carrier concentration in the not intentionally doped InGaAsSb segment is a challenge, as the data will strongly be influenced by the contact properties. Our estimation based on studies on GaSb nanowires is a level in the range from 10 17 to 10 18 cm -3 [39,40]. Devices from Sample B [28,29], used as references, had a fully doped source with an estimated carrier concentration of 10 19 cm A SEM image of a nanowire after growth can be viewed in Figure 2 In subsequent steps, the gate length was set by spin coating the sample with an organic resist (S1800) and etching the resist back to the designed thickness with reactive ion etching (RIE).…”