A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors

Brammertz, Guy; Alian, A.; Lin, Dennis; Meuris, Marc; Caymax, Matty; We, Wang

doi:10.1109/ted.2011.2165725

Cited by 104 publications

(58 citation statements)

References 17 publications

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“…This r is more than four orders of magnitude smaller than the values typically reported for interface traps in the high-k/InGaAs system. 15,20,31 This observation is in line with Ref. 32, which brings further evidence of a charge trapping process involving tunnelling into border traps.…”

Section: Transient Charging Time and Border Trap Responsesupporting

confidence: 87%

“…Recent studies have indicated the presence of border traps in high-k/InGaAs MOS structures using C-V, [15][16][17][18][19] charge pumping 20 and high-frequency transconductance 21 measurements. Evidence of the presence of border traps can also be observed in an I d -V g characteristic, where it is manifest as a hysteresis loop.…”

Section: B Evidence Of Border Trap Responsementioning

confidence: 99%

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Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Djara

Cherkaoui

Negara

et al. 2015

Journal of Applied Physics

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Original citationDjara, V., Cherkaoui, K., Negara, M. A. and Hurley, P. K. (2015) An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N inv ) from the trapped charge density in high-k/ InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I d -V g measurements enabled an accurate effective mobility vs N inv extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs. V C 2015 AIP Publishing LLC.

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Section: Transient Charging Time and Border Trap Responsesupporting

confidence: 87%

Section: B Evidence Of Border Trap Responsementioning

confidence: 99%

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Djara

Cherkaoui

Negara

et al. 2015

Journal of Applied Physics

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“…Secondly, the presence of a disordered or defective interfacial region can be considered as a rationale for the origin of accumulation dispersion. Under this consideration, interface states are located slightly far away from the dielectric/GaAs interface and can be modeled either as border traps in dielectrics near the MOS interface 51,52 or as disorder-induced gap states (DIGS) in semiconductors. 5,53 As shown in Figure 6, the incorporated nitrogen was distributed in the Al 2 O 3 layer with spatial width (identified as AlO x N y region) near the MOS interface.…”

Section: Characterization Of Electrical Properties Of Al 2 O 3 / Amentioning

confidence: 99%

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

et al. 2015

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This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm−2 eV−1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

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“…These trapping sites have been examined based on the dispersion they cause in the capacitance with ac signal frequency for In 0.53 Ga 0.47 As MOS structures biased in accumulation. [18][19][20][21] However, this dispersion can also include fast interface states aligned with energy levels in the In 0.53 Ga 0.47 As conduction band. 9,10,22 In addition to causing frequency dispersion in the measured capacitance, charge trapping sites located in the oxide can be manifest as hysteresis in the C-V response.…”

Section: Introductionmentioning

confidence: 99%

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Lin

Gomeniuk

Monaghan

et al. 2013

Journal of Applied Physics

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In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide. (C) 2013 AIP Publishing LLC

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A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors

Cited by 104 publications

References 17 publications

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

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