Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors ͑MOSFETs͒. Substrate options are overviewed. A dislocation reduction anneal Ͼ800°C decreases threading dislocation densities for Ge-on-Si wafers 10-fold to 10 7 cm −2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ϳ6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for pϩ/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H 2 anneal for device performance is shown.

In search of a proper passivation for high-k Ge metal-oxide-semiconductor devices, the authors have deposited high-k dielectric layers on GeO2, grown at 350–450°C in O2. ZrO2, HfO2, and Al2O3 were deposited by atomic layer deposition (ALD). GeO2 and ZrO2 or HfO2 intermix during ALD, together with partial reduction of Ge4+. Almost no intermixing or reduction occurs during Al2O3 ALD. Capacitors show well-behaved capacitance-voltage characteristics on both n- and p-Ge, indicating efficient passivation of the Ge∕GeOx interface. The density of interface states is typically in the low to mid-1011cm−2eV−1 range, approaching state-of-the-art Si∕HfO2∕matal gate devices.

No abstract

Au nanoparticles are efficient catalysts for the vapour-solid-liquid (VLS) growth of semiconductor nanowires, but Au poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts for Si nanowire growth can be broadened when the need for catalytic precursor dissociation is eliminated through the use of plasma enhancement. However, in this regime the incubation time for the activation of VLS growth must be minimized to avoid burying the catalyst particles underneath an amorphous Si layer. We show that the combined use of plasma enhancement and the use of a catalyst such as In, already in a liquid form at the growth temperature, is a powerful method for obtaining Si nanowire growth with high yield. Si nanowires grown by this method are monocrystalline and generally oriented in the 111 direction.

Atomic layer deposition (ALD) is used in applications where inorganic material layers with uniform thickness down to the nanometer range are required. For such thicknesses, the growth mode, defining how the material is arranged on the surface during the growth, is of critical importance. In this work, the growth mode of the zirconium tetrachloride∕water and the trimethyl aluminum∕water ALD process on hydrogen-terminated silicon was investigated by combining information on the total amount of material deposited with information on the surface fraction of the material. The total amount of material deposited was measured by Rutherford backscattering, x-ray fluorescence, and inductively coupled plasma–optical emission spectroscopy, and the surface fractions by low-energy ion scattering. Growth mode modeling was made assuming two-dimensional growth or random deposition (RD), with a “shower model” of RD recently developed for ALD. Experimental surface fractions of the ALD-grown zirconium oxide and aluminum oxide films were lower than the surface fractions calculated assuming RD, suggesting the occurrence of island growth. Island growth was confirmed with transmission electron microscopy (TEM) measurements, from which the island size and number of islands per unit surface area could also be estimated. The conclusion of island growth for the aluminum oxide deposition on hydrogen-terminated silicon contradicts earlier observations. In this work, physical aluminum oxide islands were observed in TEM after 15 ALD reaction cycles. Earlier, thicker aluminum oxide layers have been analyzed, where islands have not been observed because they have already coalesced to form a continuous film. The unreactivity of hydrogen-terminated silicon surface towards the ALD reactants, except for reactive defect areas, is proposed as the origin of island growth. Consequently, island growth can be regarded as “undesired surface-selective ALD.”

LaScO 3 , deposited by pulsed laser deposition using ceramics targets of stoichiometric composition, were studied as alternative high-k gate dielectrics on ͑100͒ Si. Their physical characterization was done using Rutherford backscattering, spectroscopic ellipsometry, x-ray diffraction, and transmission electron microscopy on blanket layers deposited on ͑100͒ Si, and electrical characterization on capacitors. It is found that DyScO 3 and GdScO 3 preserve their amorphous phases up to 1000°C. Other encouraging properties for high k applications were demonstrated, including k-value ϳ22, almost no hysteresis or frequency dispersion in C-V curves, and leakage current reduction comparable to that of HfO 2 of the same equivalent oxide thickness.

Thin insulator films of the high-κ dielectric HfO2 are deposited on Ge(100) substrates by evaporating Hf in atomic oxygen beams after in situ thermal desorption of the native oxide in ultrahigh vacuum and subsequent treatment of the clean Ge surface in oxygen and nitrogen. It is shown that HfO2 forms atomically sharp interfaces with Ge and behaves as an excellent insulator with dielectric permittivity κ∼25, which is close to the expected bulk value. Very low equivalent oxide thickness of 0.75 (±0.1) nm with a low gate leakage current of ∼4.5×10−4A∕cm2 at 1 V in accumulation is achieved. Strong frequency dispersion of the inversion capacitance and low frequency behavior of the high frequency capacitance–voltage curves is observed. This is attributed to a combined effect of a high generation rate of minority carriers due to impurity traps and the high intrinsic carrier concentration in Ge, which result in a short minority carrier response time.

Two-dimensional (2D) transition metal dichalcogenides are potential low dissipative semiconductor materials for nanoelectronic devices. Such applications require the deposition of these materials in their crystalline form and with controlled number of monolayers on large area substrates, preferably using growth temperatures compatible with temperature sensitive structures. This paper presents a low temperature Plasma Enhanced Atomic Layer Deposition (PEALD) process for 2D WS2 based on a ternary reaction cycle consisting of consecutive WF6, H2 plasma and H2S reactions. Strongly textured nanocrystalline WS2 is grown at 300 °C. The composition and crystallinity of these layers depends on the PEALD process conditions, as understood by a model for the redox chemistry of this process. The H2 plasma is essential for the deposition of WS2 as it enables the reduction of-W 6+ Fx surface species. Nevertheless, the impact of sub-surface reduction reactions needs to be minimized to obtain WS2 with well-controlled composition (S/W ratio of two).