CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

Abstract

r e b i b . The devices fabricated for this study used undoped channel Perlectly self aligned Vertical Multiple Independent Gate Field regions and doped polpilimn gates forming depletion mode transistors. Effect Transistor (MiGFET) CMOS devices have been Since the polpilimn and sourddrain regions have similar heights a single fabricated. The unique process used to fabricate these devices implant was optimized for the polpilicon gate, extension a d sourcadrain allow them to been integrated with FinFET devices. Device and regions. The devices still have very good short channel and current circuit simulations have been used to explain the device and capability due to the double gate architecture. A copper backend process explore new applications using this device. A Novel application was used to make ccntact to the two gates, source and drain. of the MIGFET as a signal mixer has been demonstrated. The Electrical Measurement and Devlce Simulation undoped channel, very thin body, perfectly matched gates allow3 (Figures 2ac) shows the electrical characteristics of the NMOS MIGFET. charge coupling of the two signals and provide a new family of When both gates are under the Same bias, the device shows double applications using the MIGFET mixer. Since the process allows gated depletion mode characteristics (Figure 2a). In this mode the device integration of regular CMOS Double gate devicas and MIGFET has all the advantages of a normal FinFET like structure it has extremely devices this technology has potential for various Digital and low leakage, DlBL and close to 6 5 m V . d~ SS. Independently biasing the Analog Mixed-Signal applications. gates of the device the threshold voltage, gain and sub-threshold swing INTRODUCTION are modulated (Figure 2 b.c). The devices show good drive and short MOSFET technologies using gates on more than one side of a channel characteristics for the case when the gates are tied together. A thin channel have shown better short channel characteristics Similar behavior is demonstrated for PMOS MIGFET devices Figure (3e and are proposed as a replacement to planar devices [I-2). c). The sub-threshold swing degradation (Figure 48) and gain (Gm) These fin type devices have a single gate wrap around multiple sensitivity (Figure 4b.c) to second gate bias demonstrate Utat this device silicon surfaces. These devices offer excellent characteristics for is extremely useful for certain applications while it will be difficult to use a given bias across the gate. Independent gate electrcdes on for other digital applications where the sub-threshold swing degradation either side of these channels however enable the channel to be substantially degrades performance. separately biased. CMP and planar Double devices have been Simulation of a 2 D cross section (Figure 5 a,b) f u an NMOS under demonstrated to offer independent dwMe gate operations [4].strong negative gate 1 potential shows a parasitic hole inversion forming The use of CMP to Pndpoint over thin fins could make all the which screens the influence of g...

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