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In short-channel silicon-on-insulator metal–oxide–semiconductor field-effect transistors, the condition for full depletion involves not only the body thickness and doping but also the channel length. The proximity of source and drain junctions reduces the apparent doping seen from the gate, which makes full depletion easier. Therefore, a transistor designed as partially depleted can behave as fully depleted. A simple analytical model for the length-doping transformation is proposed and validated by numerical simulations.

Double-gate (DG) MOSFETs promise to enhance transistor capabilities beyond the limits of conventional CMOS technology.In this paper, we study for the first time the impact of gate misalignment in "non-ideal" DG devices that may be much easier to fabricate than self-aligned versions.Drain current, transconductance, series resistance effects, subthreshold slope and carrier concentration profiles are simulated for different architectures, based on a 50nm long SOI MOSFET. We compare single gate, ideal aligned DG, and non-aligned DG transistors in which unequal gate lengths are used to compensate for the gate misalignment. We find that non-aligned DG devices are competitive with and even, in some cases, superior to ideal DG MOS, albeit with unusual g m curves.

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